Patents by Inventor Hiroshi Takeno
Hiroshi Takeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230276716Abstract: A method produces a semiconductor apparatus for a quantum computer. The apparatus includes: a semiconductor substrate; a quantum computer device formed on the semiconductor substrate; and a peripheral circuit formed on the semiconductor substrate and connected to the quantum computer device. The apparatus is to be used as a quantum computer. The method includes: a step of forming the quantum computer device and the peripheral circuit on the semiconductor substrate; and a step of deactivating a carrier in the semiconductor substrate by irradiation of a particle beam to at least a formation part for the quantum computer device and a formation part for the peripheral circuit in the semiconductor substrate. The method for producing a semiconductor apparatus for a quantum computer can produce a semiconductor apparatus for a quantum computer having excellent 3HD characteristics.Type: ApplicationFiled: May 26, 2021Publication date: August 31, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20230230926Abstract: A method for producing a semiconductor apparatus capable of producing a semiconductor apparatus with improved transmission loss characteristic using an interposer substrate in which semiconductor devices formed on a silicon single crystal substrate are connected to each other by a through electrode, the method including: a step of providing the silicon single crystal substrate containing a dopant; a step of forming the semiconductor devices and the through electrode on the silicon single crystal substrate to obtain the interposer substrate; and a step of irradiating a particle beam to at least around a formation part for the through electrode on the silicon single crystal substrate to deactivate the dopant in a region around the formation part for the through electrode.Type: ApplicationFiled: May 26, 2021Publication date: July 20, 2023Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Patent number: 10886129Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.Type: GrantFiled: July 3, 2017Date of Patent: January 5, 2021Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi Ohtsuki, Tadashi Nakasugi, Hiroshi Takeno, Katsuyoshi Suzuki
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Publication number: 20190267239Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.Type: ApplicationFiled: July 3, 2017Publication date: August 29, 2019Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Tadashi NAKASUGI, Hiroshi TAKENO, Katsuyoshi SUZUKI
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Patent number: 10297463Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.Type: GrantFiled: January 7, 2016Date of Patent: May 21, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Katsuyoshi Suzuki, Hiroshi Takeno, Koji Ebara
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Publication number: 20180247830Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.Type: ApplicationFiled: January 7, 2016Publication date: August 30, 2018Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Katsuyoshi SUZUKI, Hiroshi TAKENO, Koji EBARA
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Patent number: 9748151Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.Type: GrantFiled: February 23, 2015Date of Patent: August 29, 2017Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi Ohtsuki, Hiroshi Takeno
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Patent number: 9530702Abstract: Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a silicon substrate manufacturing process and a device manufacturing process with high accuracy. The method includes: measuring a recombination lifetime of a silicon substrate after subjecting a surface of the silicon substrate to chemical passivation processing; and performing ultraviolet protection processing of protecting at least the silicon substrate from ultraviolet rays during a period from the chemical passivation processing to a time when the measurement of the recombination lifetime is completed.Type: GrantFiled: December 27, 2013Date of Patent: December 27, 2016Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Hiroshi Takeno
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Publication number: 20160365293Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.Type: ApplicationFiled: February 23, 2015Publication date: December 15, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20160351415Abstract: A semiconductor substrate for flash lamp anneal is used in a manufacturing process of performing ion implantation to form a p-n junction on a semiconductor substrate surface and recovering an ion implantation defect by the flash lamp anneal, carbon concentration of the semiconductor substrate being 0.5 ppma or less. Consequently, it is possible to provide the semiconductor substrate for flash lamp anneal which can easily and surely prevent the ion implantation defect from remaining in a device using a flash lamp anneal process.Type: ApplicationFiled: January 26, 2015Publication date: December 1, 2016Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
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Publication number: 20160005664Abstract: Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a silicon substrate manufacturing process and a device manufacturing process with high accuracy. The method includes: measuring a recombination lifetime of a silicon substrate after subjecting a surface of the silicon substrate to chemical passivation processing; and performing ultraviolet protection processing of protecting at least the silicon substrate from ultraviolet rays during a period from the chemical passivation processing to a time when the measurement of the recombination lifetime is completed.Type: ApplicationFiled: December 27, 2013Publication date: January 7, 2016Inventor: Hiroshi Takeno
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Patent number: 8729676Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.Type: GrantFiled: April 28, 2011Date of Patent: May 20, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yutaka Shiga, Hiroshi Takeno
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Patent number: 8410573Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.Type: GrantFiled: October 20, 2008Date of Patent: April 2, 2013Assignees: DENSO CORPORATION, Shin-Etsu Handotai Co., Ltd.Inventors: Hiroshi Ohtsuki, Mitsutaka Katada, Nobuhiko Noto, Hiroshi Takeno, Kazuhiko Yoshida
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Publication number: 20130037920Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.Type: ApplicationFiled: April 28, 2011Publication date: February 14, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yutaka Shiga, Hiroshi Takeno
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Patent number: 8338277Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.Type: GrantFiled: February 19, 2008Date of Patent: December 25, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
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Patent number: 8268705Abstract: The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1×1012 atoms/cm2 or more and less than 1×1015 atoms/cm2. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.Type: GrantFiled: April 23, 2007Date of Patent: September 18, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
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Patent number: 7985660Abstract: The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p+ silicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer.Type: GrantFiled: April 16, 2008Date of Patent: July 26, 2011Assignee: Shin Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Hiroshi Takeno, Nobuhiko Noto
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Patent number: 7910455Abstract: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1×1015 atoms/cm2 or more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5° C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.Type: GrantFiled: April 16, 2007Date of Patent: March 22, 2011Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Kazuhiko Yoshida, Masao Matsumine, Hiroshi Takeno
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Patent number: 7902042Abstract: A method of manufacturing an SOI wafer includes a bonding step, a thinning and a bonding annealing step. Assuming refractive index n1 of SiO2 as 1.5, refractive index n2 of Si as 3.5, and optical thickness tOP of the silicon oxide film 2 and the SOI layer 15 in the infrared wavelength region as tOP=n1×t1+n2×t2, the thickness t1 of the silicon oxide film 2 and thickness t2 of the SOI layer so as to satisfy a relation of 0.1?<tOP<2?, and so as to make (t1×n1)/(t2×n2) fall within 0.2 to 3. By nuclei killer annealing carried out before the bonding annealing, density of formation of oxygen precipitate in the base wafer after the bonding annealing is adjusted to less than 1×109/cm3. This configuration successfully provides a method of manufacturing the SOI wafer having the thin silicon oxide film and the SOI layer, and being less likely to cause warping.Type: GrantFiled: September 9, 2005Date of Patent: March 8, 2011Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Hiroji Aga, Norihiro Kobayashi, Masayuki Imai, Tatsuo Enomoto, Hiroshi Takeno
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Publication number: 20100323502Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.Type: ApplicationFiled: February 19, 2008Publication date: December 23, 2010Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto