Patents by Inventor Hiroshi Tanimoto

Hiroshi Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4866767
    Abstract: The subscriber line interface circuit comprises subscriber nodes, reception nodes and transmission nodes, a power feeding unit, adders, impedance elements, an inverting amplifier, and a feedback element. The subscriber nodes are coupled to a subscriber terminal via a subscriber line, and the reception and transmission nodes are coupled to an exchange via a reception line and a transmission line, respectively. The feeding unit supplied a DC current to the terminal and controls the current. The first adder adds the voltage between the subscriber nodes and the voltage from the reception node. The first impedance element has an impedance corresponding to a real-number multiplication of the impedance between the subscriber nodes, and is applied with the output voltage of the first adder. The amplifier is given with the output of the first impedance element.
    Type: Grant
    Filed: August 16, 1988
    Date of Patent: September 12, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tanimoto, Minoru Tanaka, Satoru Yoshida
  • Patent number: 4803382
    Abstract: In a voltage comparator circuit, among first and second signal voltages to be compared, the first signal voltage is input to a first input terminal of a differential voltage comparator through a first switched capacitor circuit, and the second signal voltage is input to a second input terminal of the differential voltage comparator through a second switched capacitor circuit. In the voltage comparator circuit, the first and second switched capacitor circuits are matched with each other.
    Type: Grant
    Filed: December 23, 1987
    Date of Patent: February 7, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tanimoto, Mikio Hayashibara
  • Patent number: 4800339
    Abstract: An amplifier circuit has a voltage-amplifying stage, an output stage including a push-pull circuit comprising at least one complementary pair of output transistors, and a drive stage for driving the output transistors of the output stage in response to the output of the voltage-amplifying stage. The drive stage includes a subtraction unit and a signal-converting unit. The subtraction unit subtracts the output voltage of the voltage-amplifying stage, which is based on the first pole-potential of a power supply, from the reference voltage output by a reference voltage-generating unit also included in the drive stage. The subtraction unit outputs a voltage corresponding to the difference between the reference voltage and the output voltage of the voltage-amplifying stage, and supplies this voltage to the signal-converting unit. The signal-converting unit shifts the level of the input voltage, thereby producing a voltage signal based on the second pole-potential of the power supply.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: January 24, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tanimoto, Hisashi Yamada
  • Patent number: 4743872
    Abstract: A switched capacitor circuit comprises first and second switches connected in series between an input terminal and a first fixed potential terminal and third and fourth switches connected in series between an output terminal and the first fixed potential terminal. The group of the first and fourth switches and the group of the second and third switches are alternately rendered conducting and nonconducting. Two serial capacitors are connected between the junction of the first and second switches and the junction of the third and fourth switches and one parallel capacitor is connected between the junction of the two serially connected capacitors and the first fixed potential. The common junction of the three capacitors is connected to a second fixed potential terminal through a highly resistive element.
    Type: Grant
    Filed: September 19, 1986
    Date of Patent: May 10, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Tanimoto
  • Patent number: 4125674
    Abstract: Aluminum foil for an electrode of an electrolytic capacitor is disclosed. The foil comprises at least one core layer adapted to prevent the growth of pits by electrolytic etching, and outer layers formed on both surfaces of the core layer. A large number of etching pits are produced in the outer layers. In a modification, the core layer contains more iron than the outer layers. Again in a modification, the core layer is covered or contained with aluminum oxides or hydroxides.
    Type: Grant
    Filed: March 17, 1976
    Date of Patent: November 14, 1978
    Assignee: Toyo Aluminium Kabushiki Kaisha
    Inventors: Tohru Kimura, Osamu Iwao, Masahiko Kawai, Hiroshi Tanimoto
  • Patent number: 3999035
    Abstract: A lay down arc welding electrode with improved weld penetration is described. The welding electrode includes a core wire surrounded by flux, a portion of which has been longitudinally removed or has been otherwise made thinner than the flux surrounding the remainder of the arc wire. The direction of arc is adjusted by varying the shapes of core wire and flux. During welding the arc welding electrode rests on a tack weld. This causes directional angle (.alpha.) to the root of the weld to increase and the divergence angle (.beta.) to decrease, resulting in improved penetration of disposed metal. An apparatus is described for continuous lay down arc welding using the described arc welding electrode.
    Type: Grant
    Filed: May 27, 1975
    Date of Patent: December 21, 1976
    Assignee: Sumitomo Welding Electrode Co. Ltd.
    Inventors: Nobuaki Miyao, Kunihiro Kosuge, Saijiro Yoshida, Kanaaki Uchiyama, Hiroshi Tanimoto, Kazunao Mimaki, Satoru Goto