Abstract: A syndrome polynomial calculating circuit and a Reed-Solomon decoding circuit capable of performing a high-speed operation. Higher-order signals I1, I2 and I3 are inputted to first to third Galois field multiplication circuits. For each of S0, S1, S2 and S3, the multipliers are a6, a9, a12; a2, a4, a6, a8; a, a2, a3, a4. Outputs of first to third multiplication circuits and I4 are sent to an exclusive-OR gate, an output of which is sent to a D-F/F. An output of the D-F/F is sent to a fourth Galois field multiplication circuit and to an AND gate. For each of S0, S1, S2 and S3, multipliers of the fourth multiplication circuit are a4, a8, a12, a16. An output of the fourth multiplication circuit is sent to a fifth input of the exclusive OR gate. Clocks are input to the D-F/F and to a counter. The counter value is reset by the inputting of a frame pulse. The counter value is L or H for the counter value of 0 to 4 or 5, respectively. A counter output is sent to the AND gate.

Abstract: A transmission method allowing the reduced amount of hardware in a repeater is disclosed. The overhead portion of a frame is divided into a selected overhead portion for error-correction processing and the non-selected overhead portion for error-correction processing. The non-selected overhead portion such as an overhead for network management can be transferred without error-correction processing, Therefore, a repeater without error-correction processing of the non-selected overhead portion can be used and allows easy insertion and termination resulting in the reduced total amount of hardware in the repeater.

Abstract: A syndrome polynomial calculating circuit and a Reed-Solomon decoding circuit capable of performing a high-speed operation. Higher-order signals I1, I2 and I3 are inputted to first to third Galois field multiplication circuits. For each of S0, S1, S2 and S3, the multipliers are a6, a9, a12; a2, a4, a6, a8; a, a2, a3, a4. Outputs of first to third multiplication circuits and I4 are sent to an exclusive-OR gate, an output of which is sent to a D-F/F. An output of the D-F/F is sent to a fourth Galois field multiplication circuit and to an AND gate. For each of S0, S1, S2 and S3, multipliers of the fourth multiplication circuit are a4, a8, a12, a16. An output of the fourth multiplication circuit is sent to a fifth input of the exclusive OR gate. Clocks are input to the D-F/F and to a counter. The counter value is reset by the inputting of a frame pulse. The counter value is L or H for the counter value of 0 to 4 or 5, respectively. A counter output is sent to the AND gate.

Abstract: A syndrome polynomial calculating circuit and a Reed-Solomon decoding circuit capable of performing a high-speed operation. Higher-order signals I1, I2 and I3 are inputted to first to third Galois field multiplication circuits. For each of S0, S1, S2 and S3, the multipliers are a a6, a9, a12; a2, a4, a6, a8; a, a2, a3, a4. Outputs of first to third multiplication circuits and I4 are sent to an exclusive-OR gate, an output of which is sent to a D-F/F. An output of the D-F/F is sent to a fourth Galois field multiplication circuit and to an AND gate. For each of S0, S1, S2 and S3, multipliers of the fourth multiplication circuit are a4, a8, a12, a16. An output of the fourth multiplication circuit is sent to a fifth input of the exclusive OR gate. Clocks are input to the D-F/F and to a counter. The counter value is reset by the inputting of a frame pulse. The counter value is L or H for the counter value of 0 to 4 or 5, respectively. A counter output is sent to the AND gate.

Abstract: In a multiplex transmission method, a plurality of digital signals having different frame lengths and bit-synchronized at the same signal rate are transmitted after the signals are multiplexed in a predetermined order. The received multiplexed signal is demultiplexed. A predetermined sync pattern is detected from each digital signal obtained by demultiplexing. The output position of each digital signal is determined on the basis of the sync pattern detection result. A multiplex transmission system is also disclosed.

Abstract: In a Reed-Solomon encoding device which produces, for example, a Reed-Solomon code of 4 bytes for a data signal of 16 bytes, the Reed-Solomon encoding device includes a signal separating circuit (100) which separates the input signal into two signals A and B which are successively outputted in a time division fashion. In synchronism with the output of these signals, an octal counter (1) is counted up. In response to the two separated signals outputted from the signal separating circuit (100), coefficients of respective terms of a remainder obtained by dividing the data signal by a generator polynomial are classified into even-number order ones and odd-number order ones to be calculated in parallel. The even-number order coefficients and the odd-number order coefficients are supplied to selectors (2) and (3) as signals C and D, respectively.

Abstract: This invention relates to methods and apparatus for extracting data of a channel from and for inserting low speed input data into a channel of time division bit multiplex. An optical data transmission system is used for distribution of video signals or information services. A variable frequency divider generates a timing signal by frequency dividing a clock signal by N. The resulting timing signal is phase shifted by M clock periods by inserting one cycle of 1/(N+M) frequency dividing in accordance with a synchronous command signal. With the timing signal, data of a channel is extracted from the time division multiplexed data of N channels by an extracting circuit, such as a D-type flip-flop. With a synchronous signal generated from the timing signal having the same pulse width of the multiplexed data, a low speed input data is inserted into a channel of the multiplexed data of N channels by a selector.

Abstract: The size of the address space to be occupied by an expanded board installed into a slot is identified, and the corresponding relationship between an address of a computer and a slot selection signal for selecting any one of the slots is set in a mapping table on the basis of the identification result, whereby the address space to be occupied by the expanded board is adaptably allocated on an address space of the computer.

Abstract: A bath medicine is provided which comprises a water swelling gel of a natural or synthetic sodium montmorillonite or a composite of the water swelling gel and urea as the main component, and one or more components selected from among humectants, oils, fats, crude drugs, extracts, enzymes and other medicines, and which always maintains the wet state; preferably, the humectants being 1,3-butylene glycol, sodium lactate, etc., the oils and fats being jojoba oil, squalane oil, rice germ oil, etc., the crude drugs being Rehmannia root extract, peach leaf extract, loquat leaf extract, etc., the extracts being fermented rice extract, orris extract, etc., the enzymes being trypsin, papain, etc., and the other medicinal ingredients being nucleic acid, deoxyribonucleic acid, peptides obtained by the hydrolysis or enzymolysis of silkworm yarns or silk proteins, and which exhibits a remarkable effect on atopic dermatitis, pruritus cutaneus senilis, etc.

Abstract: An explosive slurry composition having excellent suspension stability, good thixotropic characteristics, high detonation power and good temperature characteristics comprises as ingredients a water-swollen gel of a complex composed of sodium montmorillonite and a water-soluble organic compound having a polar group, and an oxygen supplier such as ammonium nitrate and/or a sensitizer such as aluminum powder and/or a fuel such as saccharide, fuel oil and the like. This explosive slurry composition is used for blasting hard rocks and the like in situ connected with a booster or cap.