Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

Abstract: It is possible to obtain a semiconductor device with an element isolation structure showing a good isolation characteristic by filing an interior of a minute trench with a good quality insulating film free of a defect such as a void, and a manufacturing method therefor. The semiconductor device includes a semiconductor substrate and an isolation insulator. A trench is formed on a main surface of the semiconductor substrate. The isolation insulator is formed in an interior of the trench using a thermal oxidation method to isolate element forming regions from each other on the main surface of the semiconductor substrate. The isolation insulator is a lamination body formed by a plurality of oxide film layers.

Abstract: A manufacturing method of a semiconductor device allowing successful filling of an insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) in a gap or valley between densely placed interconnections is provided. The method includes the steps of forming semiconductor elements on a semiconductor substrate, forming on the semiconductor elements a plurality of interconnections with top protective layers side by side to electrically connect the semiconductor elements, forming a protective insulating film by CVD other than HDP-CVD to cover top and side surfaces of the interconnections and a bottom surface of a gap between the interconnections, and forming an insulating film by HDP-CVD to cover the protective insulating film and to fill in the gap between the interconnections covered with the protective insulating film.

Abstract: A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film 4 using, as a mask, a polyimide film 5 having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film 5 prior to performing anisotropic etching on a silicon oxide film 3. During the heat treatment for imidizing the polyimide film 5, since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film 5 does not come unstuck from the silicon nitride film 4. Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.

Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

Abstract: A semiconductor device allowing the manufacturing process to be simplified and fine structures therein to be readily formed and a manufacturing method thereof are provided. In the semiconductor device, a conductive layer is used as a mask during etching for forming a first opening.

Abstract: A semiconductor device having a stress-buffering film which is effective in buffering the stress caused by a molding resin during sealing, the stress-buffering film being made of a silicone ladder resin represented by formula (I) ##STR1## wherein each end group R may be the same or different and represents a hydrogen atom or an alkyl group, each side chain R' may be the same or different and represents a cyclohexyl group, a lower alkyl group, or a photopolymerizable unsaturated group, and n is an integer of 10 or larger.

Abstract: A method of manufacturing IC devices is applied in forming bumps on an electrode pads to be an input/output terminal of the ICs with a conductive metal layer interposed therebetween. Firstly, a first resist having a prescribed opening is formed over a semiconductor substrate having the electrode pads formed thereon. Thereafter, the metal layer is formed over the semiconductor substrate, and furthermore, a second resist is formed over it by making an opening in a region almost the same as the opening of the first resist. Then, the second resist is removed after forming the bumps within the opening of the second resist. Thereafter, the first resist is removed after removing an exposed portion of the metal layer. According to the processes, overetching of and generation of an etching residue of the metal layer are prevented.

Abstract: A WSI device comprises a semiconductor substrate having a wafer scale size. An integrated circuit having a unified function is formed on a main surface of the semiconductor substrate. The semiconductor substrate defines various cutouts centrally and/or peripherally thereof. The cutouts serve to extend peripheral regions of the semiconductor substrate. Bonding pads are formed along the extended peripheral regions of the semiconductor substrate. As a result, the number of bonding pads that can be formed is increased to promote multi-functioning of the WSI device.