Patents by Inventor Hiroshi TSUBOUCHI
Hiroshi TSUBOUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120548Abstract: A non-aqueous secondary battery comprising a negative electrode containing a metallic Li, a positive electrode, a separator, and an electrolyte solution, wherein the electrolyte solution contains fluorinated ethylene carbonate as a solvent in an amount of 85% by volume or more based on the total amount of the solvent, and LiPF6 as an electrolyte in an amount of 1.0 to 2.0 mol/L.Type: ApplicationFiled: July 24, 2023Publication date: April 11, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Hiroshi TSUBOUCHI
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Publication number: 20230377662Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Patent number: 11756632Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: GrantFiled: December 19, 2022Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
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Publication number: 20230119989Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Publication number: 20230062330Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: ApplicationFiled: November 11, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI, Takeshi HIOKA
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Patent number: 11562795Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.Type: GrantFiled: June 30, 2021Date of Patent: January 24, 2023Assignee: KIOXIA CORPORATIONInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
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Patent number: 11527284Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: GrantFiled: March 11, 2021Date of Patent: December 13, 2022Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi, Takeshi Hioka
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Publication number: 20220328836Abstract: An all-solid-state battery capable of improving capacity retention thereof is provided. In the all-solid-state battery having an anode active material layer, the anode active material layer contains an anode active material, a binder obtained from a material having a double bond, and a conductive material containing a material having a needle-like structure, 5 vol % to 20 vol % of the anode active material layer is the binder, and the ratio of the conductive material to the binder in terms of volume is 0.4 to 1.0.Type: ApplicationFiled: February 18, 2022Publication date: October 13, 2022Inventor: Hiroshi Tsubouchi
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Publication number: 20220238922Abstract: Provided is an all-solid battery that can reduce electrical resistance after a cycle. The all-solid battery includes a cathode layer, an anode layer, and a solid electrolyte layer. The solid electrolyte layer is formed between the cathode layer and the anode layer. The anode layer contains a Si-based active material. The Si-based active material is a secondary particle having a plurality of primary particles. When a sum of void volume inside the primary particles included in the secondary particle is set to VV1 and a sum of void volume between the primary particles included in the secondary particle is set to VV2, a ratio of the VV1 to the VV2 calculated by VV1/VV2 is 0.8 or more and 5 or less.Type: ApplicationFiled: November 3, 2021Publication date: July 28, 2022Inventor: Hiroshi Tsubouchi
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Publication number: 20210335418Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: ApplicationFiled: March 11, 2021Publication date: October 28, 2021Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI, Takeshi HIOKA
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Publication number: 20210327515Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Applicant: KIOXIA CORPORATIONInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Patent number: 11081188Abstract: According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.Type: GrantFiled: January 28, 2020Date of Patent: August 3, 2021Assignee: KIOXIA CORPORATIONInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
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Patent number: 10998337Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: GrantFiled: August 13, 2020Date of Patent: May 4, 2021Assignee: Toshiba Memory CorporationInventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
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Publication number: 20210012841Abstract: According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.Type: ApplicationFiled: January 28, 2020Publication date: January 14, 2021Applicant: KIOXIA CORPORATIONInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Publication number: 20200373326Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Applicant: Toshiba Memory CorporationInventors: Kota NISHIKAWA, Hiroshi TSUBOUCHI, Kenri NAKAI
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Patent number: 10748631Abstract: A semiconductor memory device includes a memory string with a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series. A first word line connects to the first memory cell, and a second word line connects to the second memory cell. Selection gates line are connected to first and second selection transistors. A control circuit is configured to control a write operation on the first memory string. The write operation includes a program loop with a program operation and a program verification operation. After the program loop is completed, a first voltage is applied to the first and second word lines and a second voltage is applied to the selection gate lines. The first voltage is sufficient to turn on the first and second memory cells. The second voltage is sufficient to turn on the selection transistors.Type: GrantFiled: August 22, 2018Date of Patent: August 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroshi Tsubouchi
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Patent number: 10748926Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: GrantFiled: March 12, 2019Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
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Publication number: 20200006379Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.Type: ApplicationFiled: March 12, 2019Publication date: January 2, 2020Applicant: Toshiba Memory CorporationInventors: Kota NISHIKAWA, Hiroshi TSUBOUCHI, Kenri NAKAI
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Patent number: 10490859Abstract: A positive electrode of a lithium-ion secondary battery contains first positive electrode active material particles and second positive electrode active material particles. The first positive electrode active material particles have a first composition represented by a compositional formula LiNix1Coy1Mnz1O2 (here, x1, y1, and z1 are numerical values satisfying 0<x1<1, 0<y1<1, 0.3<z1<0.5, and x1+y1+z1=1). The second positive electrode active material particles have a second composition represented by a compositional formula LiNix2Coy2Mnz2O2 (here, x2, y2, and z2 are numerical values satisfying 0<x2<1, 0<y2<1, 0<z2<0.2, and x2+y2+z2=1). The surface of at least one of the first positive electrode active material particles and the second positive electrode active material particles is coated with a transition metal oxide.Type: GrantFiled: December 11, 2017Date of Patent: November 26, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi Tsubouchi, Keiichi Takahashi, Naoyuki Wada, Yukihiro Okada
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Publication number: 20190198126Abstract: A semiconductor memory device includes a memory string with a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series. A first word line connects to the first memory cell, and a second word line connects to the second memory cell. Selection gates line are connected to first and second selection transistors. A control circuit is configured to control a write operation on the first memory string. The write operation includes a program loop with a program operation and a program verification operation. After the program loop is completed, a first voltage is applied to the first and second word lines and a second voltage is applied to the selection gate lines. The first voltage is sufficient to turn on the first and second memory cells. The second voltage is sufficient to turn on the selection transistors.Type: ApplicationFiled: August 22, 2018Publication date: June 27, 2019Inventor: Hiroshi TSUBOUCHI