Patents by Inventor Hiroshi Tsuda

Hiroshi Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120044741
    Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
    Type: Application
    Filed: June 24, 2011
    Publication date: February 23, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
  • Publication number: 20120026810
    Abstract: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.
    Type: Application
    Filed: July 28, 2011
    Publication date: February 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuji ONUMA, Kenichi HIDAKA, Hiromichi TAKAOKA, Yoshitaka KUBOTA, Hiroshi TSUDA
  • Patent number: 8095608
    Abstract: An email wrong transmission preventing apparatus calculates memory ratios of addresses of emails in a transmission log by a model expression in which the memory ratios decline over time, compiles the memory ratios of the emails for each destination to set weights, and records the weights in a user weight list. When receiving a planned outgoing email, the apparatus compares the weight of the destination of the planned outgoing email obtained by referring to the user weight list with a predetermined threshold and determines that the destination is “reliable” only if the weight is over the threshold. If even one of the destinations of the planned outgoing email is not “reliable”, the apparatus causes a sender terminal to display an address check screen to prompt address checking. When “checked” is inputted, the apparatus transfers the planned outgoing email to an email transmission server.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 10, 2012
    Assignees: Fujitsu Limited, Fujitsu Social Science Laboratory Limited
    Inventors: Ryota Fukasawa, Aya Higashizono, Natsu Hashisaka, Masayoshi Okamoto, Kiyoshi Kurashige, Hiroshi Tsuda, Yoshinori Katayama, Fumihiko Kozakura
  • Publication number: 20120002361
    Abstract: An object of the present invention is to make available a pivoting display device which enables a display unit to be assuredly stowed even by using a relatively small elastic component, and which has enhanced reliability and is space-saving. When a power switch becomes off, a monitor which can be stowed is swung by urging force from a coil spring. In an initial stage in which counter-electromotive force Vm induced by a motor is greater than on-voltage of a FET, the counter-electromotive force Vm acts as rotation resistance for the motor. When the monitor approaches a stowage position, the rotating speed of the motor is reduced. Therefore, bias voltage of the FET is reduced due to reduction of the counter-electromotive force Vm, and the braking force imposed on the motor by the counter-electromotive force Vm is gradually reduced, thereby increasing pivoting speed.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 5, 2012
    Applicant: Panasonic Corporation
    Inventors: Yusuke Tanaka, Hiroshi Tsuda
  • Publication number: 20110308778
    Abstract: An EGR cooler includes: a casing in which cooling water flows; a plurality of tubes in which exhaust gas flows, the plurality of tubes being housed in the casing; a header plate to which ends of the plurality of tubes are bonded, the header plate being bonded to an end of the casing; an inlet tank into which the exhaust gas is introduced, the inlet tank being bonded to the end of the casing; and a shielding member being provided in the inlet tank to shield a circumferential wall of the inlet tank from the introduced exhaust gas.
    Type: Application
    Filed: February 23, 2010
    Publication date: December 22, 2011
    Applicant: KOMATSU LTD.
    Inventors: Hiroshi Tsuda, Taisei Okubo, Kazuo Furuhashi, Keiichi Inaba
  • Patent number: 8080861
    Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: December 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Hiromichi Takaoka
  • Publication number: 20110272778
    Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 10, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Hiromichi Takaoka
  • Publication number: 20110264325
    Abstract: An impaired operation detection method is basically performed by sensing a yaw rate of a vehicle over a time period. Then time points are identified in which the yaw rate changes direction. A linear rate of change in the yaw rate is determined between two of the time points that are sequential in time. An actual rate of change is examined between the two time points. A difference between the actual rate of change and the linear rate of change to obtain a difference value. Then, the operator's impairment condition is determined based on the difference value.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 27, 2011
    Applicant: NISSAN TECHNICAL CENTER NORTH AMERICA, INC.
    Inventors: Shane McLaughlin, Hiroshi Tsuda, Jon Hankey, Tomohiro Yamamura, Nobuyuki Kuge
  • Publication number: 20110231607
    Abstract: A computer-implemented method that enables an operation relative to a removable storage medium connected with a computer includes, obtaining an erasing flag to be set to the removable storage medium on the basis of a predetermined rule when the removable storage medium being connected, obtaining a connection time when the removable storage medium is connected, and identifying whether a program being activated on the computer is an erasing program for erasing data stored in the removable storage medium. The computer-implemented method enables concealing, upon the erasing flag is being on and the program being activated being other than the erasing program, data to be erased classified on the basis of the connection time included in the data stored in the removable storage medium.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 22, 2011
    Applicant: Fujitsu Limited
    Inventors: Jie GAO, Toshihiro Sonoda, Shigehiro Idani, Hiroshi Tsuda
  • Publication number: 20110108923
    Abstract: A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 12, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka KUBOTA, Hiroshi TSUDA, Kenichi HIDAKA, Takuji ONUMA, Hiromichi TAKAOKA
  • Publication number: 20110067102
    Abstract: To allow inspecting whether a security check of a planned outgoing email is finished in an outgoing email check system, a check data providing apparatus 2 of an outgoing email check system 100 stores check information distributed from a check information management apparatus 1, appends check data generated based on the check information to a header of a checked planned outgoing email, and transmits the email to an email transmitting apparatus 9. A check data inspecting apparatus 3 stores the check information distributed from the check information management apparatus 1, inspects the check data extracted from the planned outgoing email received from the email transmitting apparatus 9 based on the check information, determines that the transmission is permitted when the check data of the planned outgoing email matches the check information, and determines that the transmission is rejected when the check data does not match the check information.
    Type: Application
    Filed: March 30, 2010
    Publication date: March 17, 2011
    Applicants: FUJITSU LIMITED, FUJITSU SOCIAL SCIENCE LABORATORY LIMITED
    Inventors: Ryota Fukasawa, Aya Higashizono, Natsu Hashisaka, Masayoshi Okamoto, Kiyoshi Kurashige, Hiroshi Tsuda, Yoshinori Katayama, Fumihiko Kozakura, Shinichi Mochizuki
  • Publication number: 20110019494
    Abstract: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.
    Type: Application
    Filed: June 29, 2010
    Publication date: January 27, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi TSUDA, Yoshitaka KUBOTA, Hiromichi TAKAOKA
  • Publication number: 20100251999
    Abstract: A stem is installed to an injector body and is resiliently deformable upon receiving a pressure of high pressure fuel conducted through a high pressure passage of the injector body. A strain gauge is installed to the stem to sense a strain generated in the stem. A molded IC device executes an amplifying operation, which amplifies a signal received from the strain gauge. A retainer is threadably fastened to the injector body and is configured to be rotatable relative to the stem. The stem, the strain gauge the molded IC device are integrally assembled together to form a fuel pressure sensing unit, which is installed to the injector body by threadably fastening a threaded portion of the retainer to the injector body.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 7, 2010
    Applicant: DENSO CORPORATION
    Inventors: Jun KONDO, Tomoki Fujino, Hiroshi Tsuda
  • Publication number: 20100251998
    Abstract: A stem is installed to an injector body and is resiliently deformable upon receiving a pressure of high pressure fuel conducted through a high pressure passage of the injector body. A strain gauge is installed to the stem to sense a strain generated in the stem. A molded IC device executes an amplifying operation, which amplifies a signal received from the strain gauge. The stem, the strain gauge and the molded IC device are integrally assembled together to form a fuel pressure sensing unit, which is installed to the injector body by threadably fastening a threaded portion, which is formed at the stem, to the injector body.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 7, 2010
    Applicant: DENSO CORPORATION
    Inventors: Jun KONDO, Tomoki Fujino, Hiroshi Tsuda, Yutaka Miyamoto
  • Publication number: 20100235452
    Abstract: An email wrong transmission preventing apparatus calculates memory ratios of addresses of emails in a transmission log by a model expression in which the memory ratios decline over time, compiles the memory ratios of the emails for each destination to set weights, and records the weights in a user weight list. When receiving a planned outgoing email, the apparatus compares the weight of the destination of the planned outgoing email obtained by referring to the user weight list with a predetermined threshold and determines that the destination is “reliable” only if the weight is over the threshold. If even one of the destinations of the planned outgoing email is not “reliable”, the apparatus causes a sender terminal to display an address check screen to prompt address checking. When “checked” is inputted, the apparatus transfers the planned outgoing email to an email transmission server.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 16, 2010
    Applicants: FUJITSU LIMITED, FUJITSU SOCIAL SCIENCE LABORATORY LIMITED
    Inventors: Ryota Fukasawa, Aya Higashizono, Natsu Hashisaka, Masayoshi Okamoto, Kiyoshi Kurashige, Hiroshi Tsuda, Yoshinori Katayama, Fumihiko Kozakura
  • Publication number: 20100223671
    Abstract: A document checking apparatus includes a keyword appearance position extracting unit that extracts keywords and the appearance positions of the keywords from a target document including a confidential document; a keyword pair extracting unit that treats each keyword of the appearance positions of the extracted keywords as a target and determines whether there is another extracted keyword within a predetermined range before and after the target keyword; a feature element matrix creating unit that generates, when it is determined that there is the another keyword, combination information obtained by combining the determination target keyword and the another keyword in association with anteroposterior information of the appearance positions of the keywords; and a computing unit that determines whether the number of combination information, among the plurality of combination information of the generated target document, identical to the combination information of the confidential document is not less than a prede
    Type: Application
    Filed: March 1, 2010
    Publication date: September 2, 2010
    Applicant: Fujitsu Limited
    Inventor: Hiroshi Tsuda
  • Publication number: 20100217494
    Abstract: An adaptive speed control device includes a posted speed change detecting section, a notification section, a set speed signal receiving section, and an adaptive speed control section. The posted speed change detecting section is configured to detect an upcoming change to a posted speed limit at. The notification section is configured to control a user interface device to notify a new posted speed limit at a prescribed notification timing before the vehicle reaches a transition point. The set speed signal receiving section is configured to accept a set speed signal from a user input device. The adaptive speed control section is configured to change a set speed of the vehicle according to the new posted speed limit and to automatically change a speed to the set speed upon receiving the set speed signal at or after a prescribed activation timing that occurs simultaneously with or after the prescribed notification timing.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: NISSAN TECHNICAL CENTER NORTH AMERICA, INC.
    Inventors: Ron HEFT, Hiroshi TSUDA, Hiroshi KAWAZOE, Masahide NAKAMURA
  • Publication number: 20100133650
    Abstract: A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the first interconnect and the second interconnect to connect those interconnects; a third interconnect formed on another end side thereof, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via provided in contact with the third interconnect and the second interconnect to connect those interconnects, the second via being lower in resistance than the first via. The electric fuse is disconnected by a flowing-out portion to be formed of a conductive material forming the electric fuse which flows outwardly during disconnection.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 3, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshitaka Kubota, Hiromichi Takaoka, Hiroshi Tsuda
  • Patent number: 7719689
    Abstract: There is provided a system always capable of detecting AE/ultrasound received by an FBG, even when the FBG receives a change in temperature or strain and the Bragg wavelength is fluctuated. In the AE/ultrasound detection system, the reflected light from the FBG is caused to enter a Fabry-Perot filter having an FSR equal to or greater than the reflection wavelength band of the FBG. A change in the intensity of the transmitted light corresponds to the AE/ultrasound received by the FBG. Alternatively, the reflected light from FBG is caused to enter two Fabry-Perot filters having an FSR equal to or greater than the reflection wavelength band of the FBG and having the filter-transmittance peak wavelengths different from each other by FSR/4. The intensity of the transmitted light from each of the two Fabry-Perot filters is converted into a voltage signal, and the individual signals are subjected to addition and subtraction processes.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: May 18, 2010
    Assignees: National Institute of Advanced Industrial Science & Technology, Ishikawajima Inspection & Instrumentation Co., Ltd
    Inventors: Jung-Ryul Lee, Hiroshi Tsuda, Takahiro Arakawa, Tomio Nakajima
  • Publication number: 20100096723
    Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 22, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Hiromichi Takaoka