Patents by Inventor Hiroshi Tsutsu

Hiroshi Tsutsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7306980
    Abstract: A number of minuscule LDD thin film transistors with high precision are arranged on a substrate for use in a liquid crystal display apparatus or other similar devices. The gate electrode is used as a mask at the time of injecting impurities into the semiconductor layer. To realize an LDD structure, the impurities are injected in two installments. The size of the gate electrode is changed in accordance with the length of the LDD regions between the first and second injections. The size of the gate electrode is changed by means of metal oxidation or dry etching. For precision dry etching of the gate electrode, various ideas are put into forming the photo resist.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: December 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shin-itsu Takehashi, Tetsuo Kawakita, Yoshinao Taketomi, Hiroshi Tsutsu
  • Patent number: 7256757
    Abstract: An organic EL display panel includes a substrate, pixel electrodes, a common electrode, signal lines, power supply lines, thin-film transistors, scan lines, organic EL elements and storage capacitors. To obtain a full color image by light emissions of the organic EL elements, red, green and blue emitters are patterned correspondently with the pixel electrodes and arranged in this order along the gate line direction. The emitters are patterned such that each pair of the red, green and blue emitters which are adjacent to each other along the gate line direction overlap each other to define a light-emitting layer overlap region, where colors of light components which exit the organic EL elements and pass through the emitters are mixed, between the adjacent organic EL elements arranged along the gate line direction. At least one of the thin-film transistor and the storage capacitor is arranged in the light-emitting layer overlap region.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 14, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Yutaka Nanno, Hiroshi Tsutsu
  • Patent number: 7061453
    Abstract: A unit pixel (10) includes a plurality of current controlling elements (Tr2a–Tr2d) having controlling terminal and connected to a single EL element (11), and switching elements (Tr1a–Tr1d) provided to the respective current controlling elements in order to switch between application and cutoff of a digital image signal with respect to the controlling terminals in accordance with the condition of a scanning signal. Each of the current controlling elements is controlled by a voltage of the digital image signal so as to take an OFF state for cutting off a supply of a driving current to the EL element or an ON state for supplying the EL element with a driving current corresponding to the voltage of the digital image signal, and a value of the current flowing in the EL element is the sum value of currents supplied from the respective current controlling elements in the ON state.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouji Senda, Yutaka Nanno, Hiroshi Tsutsu
  • Patent number: 6974972
    Abstract: In a large-sized substrate for use in liquid crystal display devices, microcracks in a gate insulating film are prevented from being generated, whereby warpage of the substrate is suppressed. In order to solve the problems, in thin film transistors arrayed on a glass substrate, the gate insulating film is made thicker only in the portion that is directly under a gate line layer.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hironori Tanaka, Hiroshi Tsutsu
  • Publication number: 20050224799
    Abstract: A semiconductor device provided with a thin-film transistor comprising a polycrystalline semiconductor thin film (2) formed on an insulating substrate (100). The semiconductor device comprises a channel region (80), a source region (91), and a drain region (92), each disposed on both sides of the channel region (80) in the semiconductor thin film (100). The channel region (90) comprises both a first conductive impurity and a second conductive impurity, the conductive type of the second conductive impurity being opposite the conductive type of the first conductive impurity, and is structured by layering a first layer in which the first conductive impurity and the second conductive impurity are canceled and a second layer in which either of the first conductive impurity or the second conductive impurity is dominant, wherein a gate electrode (4) is formed so as to face the first layer (2a) via an insulating film (3).
    Type: Application
    Filed: February 7, 2002
    Publication date: October 13, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinichi Yamamoto, Nishio Mikio, Tetsuo Kawakita, Hiroshi Tsutsu
  • Publication number: 20050212449
    Abstract: An organic EL display panel includes a substrate, pixel electrodes, a common electrode, signal lines, power supply lines, thin-film transistors, scan lines, organic EL elements and storage capacitors. To obtain a full color image by light emissions of the organic EL elements, red, green and blue emitters are patterned correspondently with the pixel electrodes and arranged in this order along the gate line direction. The emitters are patterned such that each pair of the red, green and blue emitters which are adjacent to each other along the gate line direction overlap each other to define a light-emitting layer overlap region, where colors of light components which exit the organic EL elements and pass through the emitters are mixed, between the adjacent organic EL elements arranged along the gate line direction. At least one of the thin-film transistor and the storage capacitor is arranged in the light-emitting layer overlap region.
    Type: Application
    Filed: May 25, 2005
    Publication date: September 29, 2005
    Inventors: Yutaka Nanno, Hiroshi Tsutsu
  • Publication number: 20040229415
    Abstract: A number of minuscule LDD thin film transistors with high precision are arranged on a substrate for use in a liquid crystal display apparatus or other similar devices. The gate electrode is used as a mask at the time of injecting impurities into the semiconductor layer. To realize an LDD structure, the impurities are injected in two installments. The size of the gate electrode is changed in accordance with the length of the LDD regions between the first and second injections. The size of the gate electrode is changed by means of metal oxidation or dry etching. For precision dry etching of the gate electrode, various ideas are put into forming the photo resist.
    Type: Application
    Filed: June 21, 2004
    Publication date: November 18, 2004
    Applicant: Matsushita Elec. Ind. Co. Ltd.
    Inventors: Shin-itsu Takehashi, Tetsuo Kawakita, Yoshinao Taketomi, Hiroshi Tsutsu
  • Patent number: 6806498
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: October 19, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Publication number: 20040196218
    Abstract: A unit pixel (10) includes a plurality of current controlling elements (Tr2a-Tr2d) having controlling terminal and connected to a single EL element (11), and switching elements (Tr1a-Tr1d) provided to the respective current controlling elements in order to switch between application and cutoff of a digital image signal with respect to the controlling terminals in accordance with the condition of a scanning signal. Each of the current controlling elements is controlled by a voltage of the digital image signal so as to take an OFF state for cutting off a supply of a driving current to the EL element or an ON state for supplying the EL element with a driving current corresponding to the voltage of the digital image signal, and a value of the current flowing in the EL element is the sum value of currents supplied from the respective current controlling elements in the ON state.
    Type: Application
    Filed: December 23, 2003
    Publication date: October 7, 2004
    Inventors: Kouji Senda, Yutaka Nanno, Hiroshi Tsutsu
  • Patent number: 6528397
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203 is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko MIno
  • Publication number: 20030022471
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203. is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Patent number: 6411273
    Abstract: An object of the present invention is, by eliminating a driver IC from the components of an liquid crystal display, to achieve a cost reduction, to eliminate a manufacturing step of mounting the driver IC onto an array substrate, and to reduce a thickness of the liquid crystal display. A driver circuit for an active matrix liquid crystal display comprises a resistive dividing type digital-to-analog converter circuit (DAC). An analog output voltage from the DAC is amplified by a signal amplifier element, and a liquid crystal element is driven by the amplified analog output voltage. The driver circuit is characterized in that a resistance element R is formed in an n+ layer of p-Si on an array substrate of the liquid crystal display, and a switching element Tr and a signal amplifier element are also formed on the array substrate.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: June 25, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mika Nakamura, Yutaka Nanno, Naomi Kaneko, Masumi Izuchi, Hiroshi Tsutsu, Katsumi Adachi
  • Patent number: 6228692
    Abstract: A thin film semiconductor device includes: a substrate having an insulating surface; a semiconductor layer containing silicon and germanium formed on the substrate; a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a thermal oxide film formed by thermally oxidizing a surface of the semiconductor layer.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: May 8, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroshi Tsutsu
  • Patent number: 6118151
    Abstract: A thin film semiconductor device includes: a substrate having an insulating surface; a semiconductor layer containing silicon and germanium formed on the substrate; a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a thermal oxide film formed by thermally oxidizing a surface of the semiconductor layer.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: September 12, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroshi Tsutsu
  • Patent number: 5766989
    Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: June 16, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeki Maegawa, Mamoru Furuta, Hiroshi Tsutsu, Tetsuya Kawamura, Yutaka Miyata
  • Patent number: 5622814
    Abstract: A method for fabricating an active matrix substrate for forming constituent elements such as a semiconductor layer, a passivation layer, an electrode material and other elements, uses a photoresist exposed from the reverse side of the substrate, using the gate electrode pattern made of opaque material on a transparent substrate as the mask. This method contributes to lowering the cost and improving the performance of semiconductor devices.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Miyata, Tetsuya Kawamura, Hiroshi Tsutsu
  • Patent number: 5351145
    Abstract: An active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to the n-type and p-type transistors for controlling the n-type and p-type transistors, and pixel-corresponding electrodes controlled by the transistor pairs respectively. Drains of an n-type transistor and a p-type transistor in each of the pairs are connected to each other via a related pixel corresponding electrode. First pulses are applied to gates of the n-type transistors. Second pulses are applied to gates of the p-type transistors. There is provided a difference in phase between the first pulses and the second pulses.
    Type: Grant
    Filed: January 9, 1992
    Date of Patent: September 27, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Miyata, Mamoru Furuta, Tatsuo Yoshioka, Hiroshi Tsutsu, Tetsuya Kawamura
  • Patent number: 5056897
    Abstract: A spatial light modulator and a neural network circuit are disclosed. The modulator is used in pattern recognition and has an arrangement in which a photoconductive layer held between conductive electrodes is connected in series to a liquid crystal cell including a liquid crystal layer held between two opposite electrodes. Setting the rate between the area of the photoconductive layer and the area of at least one of the opposite electrodes between which the liquid crystal layer is disposed, provides a highly efficient reflective and transmissive spatial light modulator of a simple structure. Both reflective and transmissive spatial light modulating elements are applied to a neurocomputer or the like.
    Type: Grant
    Filed: November 22, 1989
    Date of Patent: October 15, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Akiyama, Hiroshi Tsutsu, Tetsu Ogawa, Hiroshi Tsutsui