Abstract: A machine learning system includes a learning section and an operating section including a memory. The operating section holds a required accuracy, and an internal state and a weight value of a learner in the memory and executes calculation processing by using data input to the machine learning system and the weight value held in the memory to update the internal state. An accuracy of the internal state is calculated from a result of the calculation processing and an evaluation value is calculated using the data input to the machine learning system, the weight value, and the updated internal state held in the memory when the calculated accuracy is higher than the required accuracy. The evaluation value is transmitted to the learning section, which updates the weight value by using the evaluation value and notifies the number of times of updating the weight value to the operating section.

Abstract: A machine learning system includes a learning section and an operating section including a memory. The operating section holds a required accuracy, and an internal state and a weight value of a learner in the memory and executes calculation processing by using data input to the machine learning system and the weight value held in the memory to update the internal state. An accuracy of the internal state is calculated from a result of the calculation processing and an evaluation value is calculated using the data input to the machine learning system, the weight value, and the updated internal state held in the memory when the calculated accuracy is higher than the required accuracy. The evaluation value is transmitted to the learning section, which updates the weight value by using the evaluation value and notifies the number of times of updating the weight value to the operating section.

Abstract: An image recognition system includes an external information detection unit detecting a distance to a target to be recognized included in an image, a reduced image size determination unit deriving a reduced size of the image based on the distance to the target to be recognized, an image reduction unit reducing the image based on the reduced size of the image, and an image recognition unit including a plurality of recognition process units corresponding to sizes of the images to be recognized and executing the recognition process of the target to be recognized included in the reduced image by means of the recognition process unit corresponding to a size of the image. Instead of the distance to the target to be recognized, a size and a shape of the image, or a clip position of the image from an entire image, may be used.

Abstract: Provided is a machine learning system aimed at achieving power saving and circuit scale reduction of learning and inference processing in machine learning. The machine learning system includes a learning unit, a data extraction unit, and a data processing unit. The learning unit includes an internal state and an internal parameter. The data extraction unit creates processing input data by removing a part which does not affect an evaluation value calculated by the data processing unit from an input data input in the machine learning system. The data processing unit calculates an evaluation value based on the processing input data and the learning unit. The input data includes discrete values, and an internal state changes according to a change of the input data.

Abstract: An image recognition system includes an external information detection unit detecting a distance to a target to be recognized included in an image, a reduced image size determination unit deriving a reduced size of the image based on the distance to the target to be recognized, an image reduction unit reducing the image based on the reduced size of the image, and an image recognition unit including a plurality of recognition process units corresponding to sizes of the images to be recognized and executing the recognition process of the target to be recognized included in the reduced image by means of the recognition process unit corresponding to a size of the image. Instead of the distance to the target to be recognized, a size and a shape of the image, or a clip position of the image from an entire image, may be used.

Abstract: An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Abstract: An information processing apparatus including a memory subsystem connected to a host to perform arithmetic processing, where the host notifies a write request including data and a type of the data to the memory subsystem, and, based on a first memory, a second memory which has a size of a data erase unit, for erasing data, larger than a size of a write unit of the data and a data capacity larger than that of the first memory, and the type of the data, the memory subsystem writes random access data and data other than the random access data in different erase units of the second memory.

Abstract: An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Abstract: An information processing device includes a host and a memory subsystem. The host issues a write command or an erase command with tag information corresponding to data to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory, a second memory, and a memory subsystem control circuit. The first memory stores management information for managing the second memory. The second memory has a larger size of a data erase unit than a size of a data write unit and stores the data. The memory subsystem control circuit writes data on the same tag information in the same management unit and writes data on the different tag information in the different management unit, based on the management information in which n times of the data erase unit (“n” is a natural number) is a management unit.

Abstract: A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.

Abstract: The information processing apparatus includes a preprocessing unit that allocates the identifier to one or more collected groups, the main storage unit including a buffer having a size of the predetermined unit installed for each group, the storage unit that stores the data written in the buffer for each predetermined unit and each group, a write processing unit that acquires the data allocated to the group for each group and writes the acquired data in the buffer, determines whether or not the data of the predetermined unit has been written in the buffer, and causes the storage unit to store the data written in the buffer when the data of the predetermined unit is determined to have been written in the buffer, and a read processing unit that reads the stored data out to the main storage unit for each group, extracts the read data, and executes the process.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A first objective is to reduce performance degradation of a semiconductor storage resulting from address translation. A second objective is to reduce an increase in the manufacturing cost of the semiconductor storage resulting from address translation. A third objective is to provide the semiconductor storage with high reliability. To accomplish the above objectives, a storage area of a nonvolatile memory included in the semiconductor storage is segmented into multiple blocks, and each of the blocks is segmented into multiple pages. Then, an erase count is controlled on a page basis (109), and address translation is controlled on a block basis (108).

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.

Abstract: In a storage device system having a plurality of memory modules including a non-volatile memory, improved reliability and a longer life or the like is to be realized. To this end, a plurality of memory modules (STG) notifies a control circuit DKCTL0 of a write data volume (Wstg) that is actually written in an internal non-volatile memory thereof. The control circuit DKCTL0 finds a predicted write data volume (eWd) for each memory module on the basis of the write data volume (Wstg), a write data volume (Wh2d) involved in a write command that is already issued to the plurality of memory modules, and a write data volume (ntW) involved in a next write command. Then, a next write command is issued to the memory module having the smallest predicted write data volume.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.