Patents by Inventor Hiroshi Ueki

Hiroshi Ueki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127528
    Abstract: A coil component includes a device main body composed of an insulator, a coil conductor which is disposed inside or on a surface of the device main body, and an outer electrode which is disposed on a surface of the device main body and electrically connected to the coil conductor. The outer electrode includes a Ag-containing layer containing Ag grains with an average grain size of 4.2 to 15 ?m.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 21, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiichi Tsuduki, Kouhei Matsuura, Hiroshi Ueki
  • Publication number: 20210241970
    Abstract: A common-mode choke coil includes a multilayer body, a first coil, and a second coil. The multilayer body includes plural stacked non-conductor layers. The first and second coils are incorporated in the multilayer body. The first coil includes a first coil conductor. The second coil includes a second coil conductor disposed along an interface between non-conductor layers different from an interface between non-conductor layers along which the first coil conductor is disposed. With the first coil conductor and the second coil conductor being viewed in plan in the stacking direction of the multilayer body, the first coil conductor and the second coil conductor have no portion where the two coil conductors overlap each other, except for a portion where the two coil conductors cross each other.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kouhei MATSUURA, Atsuo HIRUKAWA, Hiroshi UEKI
  • Publication number: 20210241958
    Abstract: A common-mode choke coil includes a multilayer body, a first coil, and a second coil. The multilayer body is a cuboid in shape that includes plural stacked non-conductor layers. The first and second coils are incorporated in the multilayer body. The first coil includes a first coil conductor, and the second coil includes a second coil conductor. The first coil conductor is positioned with gaps SG1 to SG4 interposed between the first coil conductor and the outer periphery surface of the multilayer body. The second coil conductor is positioned with gaps SG5 to SG8 interposed between the second coil conductor and the outer periphery surface of the multilayer body. Of the four absolute values of the differences between the gaps SG1 to SG4 and the corresponding gaps SG5 to SG8, at least two absolute values are greater than or equal to 0.02 mm.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kouhei MATSUURA, Atsuo HIRUKAWA, Hiroshi UEKI
  • Publication number: 20210241959
    Abstract: A common-mode choke coil includes a multilayer body, and first and second coils incorporated in the multilayer body. The multilayer body is a cuboid shape including plural stacked non-conductor layers. The first coil includes a first coil conductor. The second coil includes a second coil conductor. With the common-mode choke coil, in a frequency region greater than or equal to 0.1 GHz and less than or equal to 100 GHz (i.e., from 0.1 GHz to 100 GHz), the Sdd21 transmission characteristic is less than or equal to ?3 dB at or above 30 GHz, and in a frequency region greater than or equal to 10 GHz and less than or equal to 60 GHz (i.e., from 10 GHz to 60 GHz), the Scc21 transmission characteristic is minimum at or above 20 GHz, and the Scc21 transmission characteristic has a minimum value of less than or equal to ?20 dB.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kouhei MATSUURA, Atsuo HIRUKAWA, Hiroshi UEKI
  • Publication number: 20210241969
    Abstract: A common-mode choke coil includes a multilayer body, a first coil, a second coil, a first terminal electrode, a second terminal electrode, a third terminal electrode, and a fourth terminal electrode. The multilayer body includes plural non-conductor layers. The first and second coils are incorporated in the multilayer body. The first and second terminal electrodes are connected to the first coil. The third and fourth terminal electrodes are connected to the second coil. The first coil has a path length L1, the second coil has a path length L2, and the sum of the path length L1 and the path length L2 is less than or equal to 3.5 mm.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kouhei MATSUURA, Atsuo HIRUKAWA, Hiroshi UEKI
  • Publication number: 20210241957
    Abstract: A common-mode choke coil includes a multilayer body, a first coil, a second coil, a first terminal electrode, a second terminal electrode, a third terminal electrode, and a fourth terminal electrode. The multilayer body includes plural non-conductor layers. The first and second coils are incorporated in the multilayer body. The first and second terminal electrodes are connected to the first coil. The third and fourth terminal electrodes are connected to the second coil. The first coil includes a first coil conductor. The second coil includes a second coil conductor disposed along an interface between non-conductor layers different from an interface between non-conductor layers along which the first coil conductor is disposed. The first and second coil conductors each have a number of turns of less than 2.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kouhei MATSUURA, Atsuo HIRUKAWA, Hiroshi UEKI
  • Publication number: 20190206612
    Abstract: A coil component includes a device main body composed of an insulator, a coil conductor which is disposed inside or on a surface of the device main body, and an outer electrode which is disposed on a surface of the device main body and electrically connected to the coil conductor. The outer electrode includes a Ag-containing layer containing Ag grains with an average grain size of 4.2 to 15 ?m.
    Type: Application
    Filed: December 17, 2018
    Publication date: July 4, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Keiichi TSUDUKI, Kouhei MATSUURA, Hiroshi UEKI
  • Patent number: 10268576
    Abstract: An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueki, Eiji Koeta
  • Patent number: 10152456
    Abstract: A correlation operation circuit includes a first SRAM storing a plurality of pieces of detection pattern data, product-sum operators, a second SRAM storing intermediate data, and a comparator. When time series data is sequentially input, the intermediate data of all correlation functions referring to one time series data in a period during which the one time series data is input. When one time series data is input, the product-sum operator multiplies the detection pattern data sequentially read from the first SRAM by the one input time series data. The corresponding intermediate data is read from the second SRAM in synchronization with the multiplication, and the sequentially-calculated products are cumulatively added to the read intermediate data to be written back into the second SRAM as the intermediate data. As a result, the calculated correlation function data is supplied to the comparator to be compared with a predetermined specified value.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Ueki
  • Publication number: 20180341581
    Abstract: An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance.
    Type: Application
    Filed: March 7, 2018
    Publication date: November 29, 2018
    Inventors: Hiroshi Ueki, Eiji Koeta
  • Publication number: 20170337158
    Abstract: A correlation operation circuit includes a first SRAM storing a plurality of pieces of detection pattern data, product-sum operators, a second SRAM storing intermediate data, and a comparator. When time series data is sequentially input, the intermediate data of all correlation functions referring to one time series data in a period during which the one time series data is input. When one time series data is input, the product-sum operator multiplies the detection pattern data sequentially read from the first SRAM by the one input time series data. The corresponding intermediate data is read from the second SRAM in synchronization with the multiplication, and the sequentially-calculated products are cumulatively added to the read intermediate data to be written back into the second SRAM as the intermediate data. As a result, the calculated correlation function data is supplied to the comparator to be compared with a predetermined specified value.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 23, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Hiroshi UEKI
  • Publication number: 20170177062
    Abstract: According to one embodiment, a semiconductor device includes an operation circuit 20 that calculates an expected value ?? of a new waiting time based on a measured value z of a waiting time of an apparatus to be controlled 15 that varies depending on a timing when an interruption signal is generated and an expected value ? of the waiting time, and a waiting mode control circuit 12 that sets a waiting state when the apparatus to be controlled 15 is waiting to a waiting state in accordance with the expected value ?? of the new waiting time.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 22, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Hiroshi UEKI
  • Publication number: 20170076102
    Abstract: A semiconductor device capable of arbitrarily operating a microprocessor while protecting a secure program is provided. The semiconductor device includes a memory equipped with a first program area in which an arbitrary program is stored, and a second program area in which a secure program is stored, a microprocessor which outputs an address designating an instruction in a program, and a memory protection unit which controls access to the memory based on the address outputted from the microprocessor. When the address outputted from the microprocessor by executing the program in the first program area designates a branch allowable area in the second program area, the memory protection unit permits access to the memory. When the address designates a branch prohibition area, the memory protection unit inhibits access to the memory.
    Type: Application
    Filed: July 19, 2016
    Publication date: March 16, 2017
    Inventors: Kuniyasu ISHIHARA, Hiroshi UEKI
  • Patent number: 9344101
    Abstract: In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: May 17, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi Ueki
  • Publication number: 20160056828
    Abstract: In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventor: Hiroshi UEKI
  • Publication number: 20150161307
    Abstract: The present invention provides a method of designing a semiconductor device capable of executing a DVFS control which minimizes consumption energy. A consumption power profile P(t) when a known operating voltage and a clock of a known frequency are given to a logic circuit as a DVFS target and a process as a DVFS target is executed is obtained. The obtained power profile is converted to a function related to a clock cycle q(t), and a load capacity of the target logic circuit is obtained as a function of the clock cycle q(t). An operating voltage and an operating frequency are calculated as functions (V(q), f(q)) for a clock cycle so as to satisfy a condition using, as a constant, a product (C(q)·(dq/dt){circle around ( )}3) of the load capacity function and cube of time differentiation of the clock cycle. The calculated functions of the operating voltage and the operating frequency are solutions of the Euler equation according to the calculus of variations, and consumption energy is minimized.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 11, 2015
    Inventor: Hiroshi UEKI
  • Patent number: 8802506
    Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable silicone composition which is fed into the space between the mold and the unsealed semiconductor device to compression molding, the method being characterized by the fact that the aforementioned curable silicone composition comprises at least the following components: (A) an epoxy-containing silicone and (B) a curing agent for an epoxy resin; can reduce warping of the semiconductor chips and circuit board, and improve surface resistance to scratching.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 12, 2014
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Minoru Isshiki, Tomoko Kato, Yoshitsugu Morita, Hiroshi Ueki
  • Patent number: 8674037
    Abstract: A silicon-containing polymer represented by the following average unit formula: (O2/2SiR1-R2-C6H4-R2-SiR1O2/2)x [R3 SiO(4-a)/2]y(R4O1/2)z (wherein R1 designates identical or different, substituted or unsubstituted monovalent hydrocarbon groups; R2 designates identical or different, substituted or unsubstituted alkylene groups; R3 designates substituted or unsubstituted monovalent hydrocarbon groups; R4 designates alkyl groups or hydrogen atoms; ‘a’ is a positive number that satisfies the following condition: 0=a=3; and ‘x’, ‘y’, and ‘z’ are positive numbers that satisfy the following conditions: 0<x<0.1; 0<y<1; 0=z<0.1; and (x+y+z)=1); and a curable polymer composition comprising: (A) the aforementioned silicon-containing polymer; (B) an organosilicon compound that contains in one molecule at least two silicon-bonded hydrogen atoms; and (C) a hydrosilylation catalyst.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: March 18, 2014
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Yoshitsugu Morita, Yoshinori Taniguchi, Hiroshi Ueki
  • Patent number: 8563666
    Abstract: A curable silicone composition comprising: (A) a liquid organopolysiloxane having in one molecule at least two epoxy groups; (B) a compound containing groups that react with the epoxy groups; (C) a thermally conductive filler; and (D) a silicone powder, preferably, an epoxy-containing silicone powder; possesses excellent handleability and workability in combination with low viscosity and that, when cured, forms a cured body of excellent elasticity, adhesiveness, and thermal conductivity.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: October 22, 2013
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Yoshitsugu Morita, Hiroshi Ueki
  • Patent number: 8309652
    Abstract: A curable silicone composition comprising: (A) an organopolysiloxane that is represented by the average unit formula: (R13SiO1/2)a(R22SiO2/2)b(R3SiO3/2)c(SiO4/2)d (wherein R1, R2, and R3 are each independently selected from substituted or unsubstituted monovalent hydrocarbon groups and epoxy-functional monovalent organic groups, with the proviso that at least 20 mole % of R3 are aryl groups, and a, b, c, and d are numbers that satisfy 0?a?0.8, 0?b?0.8, 0.2?c?0.9, 0?d<0.8, and a+b+c+d=1), and that has at least two of the aforementioned epoxy-functional monovalent organic groups in each molecule; (B) a compound that has a group capable of reacting with the epoxy group; (C) a cure accelerator; and (D) a thermally conductive filler, has excellent handling characteristics and that cures rapidly to give a cured product that is highly thermally conductive, very flexible, highly adhesive, and very flame retardant.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 13, 2012
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Yoshitsugu Morita, Minoru Isshiki, Hiroshi Ueki