Abstract: An optical module according to the present disclosure includes a glass substrate having a first surface, a second surface opposite to the first surface, and a via hole connecting the first surface and the second surface each other; an optical element mounted on the first surface of the glass substrate and joined to the via hole of the glass substrate, the optical element being configured to consume an electricity and perform at least one of an input and an output of an optical signal; a temperature control element mounted on the second surface of the glass substrate and joined to the via hole of the glass substrate, the temperature control element being configured to regulate a temperature of the optical element; and a first housing attached to the first surface, the first housing being configured to hermetically seal the optical element.

Abstract: A rear sprocket comprises a sprocket body, a plurality of sprocket teeth, a plurality of spline teeth, a maximum spline distance, and a radial tooth-bottom distance. Each of the plurality of spline teeth has a spline crest. The maximum spline distance is defined from the rotational center axis to the spline crest. The radial tooth-bottom distance is defined from a rotational center axis to one of plurality of tooth bottom center points. The maximum spline distance is larger than the radial tooth-bottom distance. The spline crest of each of the plurality of spline teeth is positioned radially inwardly from the tooth outline of each of the plurality of sprocket teeth in the radial direction.

Abstract: A driving circuit includes first and second input signal terminals, first and second output signal terminals, constant current sources, first and second transistors having control terminals connected to the first and second input signal terminals, third and fourth transistors each having a control terminal to which a first bias voltage is applied, first and second inductors each having a first inductance, and third and fourth inductors each having a second inductance larger than the first inductance. The driving circuit further includes fifth and sixth transistors each having a control terminal to which a second bias voltage is applied, outflow terminals connected to inflow terminals of the third and fourth transistors via the first and second inductors, and inflow terminals connected to the first and second output signal terminals via the third and fourth inductors.

Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.

Abstract: An output circuit includes: an inductor, an amplifier circuit that outputs an output signal via the inductor, an output terminal that outputs the output signal to an outside, a voltage divider circuit including a series circuit constituted by a first capacitive element and a second capacitive element connected in series to the first capacitive element, the series circuit generating a first voltage-divided signal by dividing a voltage of the output signal, a first band-adjusting element having a resistance component for generating a first band-adjusted signal by adjusting frequency characteristics of the first voltage-divided signal, and a first peak detection circuit that detects a peak voltage of the first band-adjusted signal and output a first peak voltage in accordance with the detected peak voltage.

Abstract: An optical module includes: a housing having a first face and a second face parallel to the first face; a first block fixed to the first face of the housing by a first adhesive; an integrated circuit (IC) fixed to the first block by a second adhesive having a thickness larger than a thickness of the first adhesive; a thermoelectric cooler (TEC) fixed to the second face of the housing; an optical circuit element fixed to the TEC; and an interconnection board mounted on the IC and the optical circuit element, the interconnection board being configured to electrically couple the IC to the optical circuit element. The first block is sandwiched between the housing and the IC. The TEC is sandwiched between the housing and the optical circuit element.

Abstract: According to one embodiment, an optical module includes: a lid having a first face and a second face, the lid including a bump, a wiring, and a through via; an optical circuit element; a first integrated circuit (IC); a first block bonded to the first IC by a first adhesive; a temperature control element bonded to the optical circuit element; and a housing having an opening and a third face provided inside the opening, the housing being configured to house the first IC, the optical circuit element, the first block, and the temperature control element, the third face being bonded to the first block and the temperature control element by a second adhesive, the housing being hermetically sealed with the lid.

Abstract: An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.

Abstract: A driving circuit includes first and second input signal terminals, first and second output signal terminals, constant current sources, first and second transistors having control terminals connected to the first and second input signal terminals, third and fourth transistors each having a control terminal to which a first bias voltage is applied, first and second inductors each having a first inductance, and third and fourth inductors each having a second inductance larger than the first inductance. The driving circuit further includes fifth and sixth transistors each having a control terminal to which a second bias voltage is applied, outflow terminals connected to inflow terminals of the third and fourth transistors via the first and second inductors, and inflow terminals connected to the first and second output signal terminals via the third and fourth inductors.

Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.

Abstract: An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a common node, a second diode circuit connected between the second output terminal and the common node, an intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at the common node, an intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, and a clamp circuit configured to electrically connect the common node to a ground line in accordance with the intermediate voltage.

Abstract: An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.

Abstract: A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.

Abstract: According to an embodiment, a circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first control terminal to receive a first input signal, a first current terminal to output an inverted output signal, and a second current terminal. The second transistor includes a second control terminal to receive a second input signal, a third current terminal to output a non-inverted output signal, and a fourth current terminal connected to the second current terminal. The third transistor includes a third control terminal to receive the inverted output signal, a fifth current terminal electrically connected to the second and fourth current terminals, and a sixth current terminal electrically connected to a first power supply.

Abstract: According to one embodiment, an optical device includes an optical element and a via. The optical element is provided directly on a second main surface opposed to a first main surface of a semiconductor substrate. The via is aligned with the optical element and formed to extend halfway in a thickness direction from the first main surface of the semiconductor substrate.

Abstract: According to one embodiment, the silicon substrate includes a thinned portion and a side wall provided around the thinned portion. The thinned portion is thinned selectively from one surface. The optical element is formed on a surface of the thinned portion. The surface of the thinned portion is opposite to the one surface of the silicon substrate. The light guide member includes a lens portion, a light guide portion, and an alignment portion. The light guide portion is provided between the lens portion and the optical element. The alignment portion is for an optical connector. The thinned portion of the silicon substrate is provided between the light guide portion of the light guide member and the optical element.

Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

Abstract: According to an embodiment, a circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first control terminal to receive a first input signal, a first current terminal to output an inverted output signal, and a second current terminal. The second transistor includes a second control terminal to receive a second input signal, a third current terminal to output a non-inverted output signal, and a fourth current terminal connected to the second current terminal. The third transistor includes a third control terminal to receive the inverted output signal, a fifth current terminal electrically connected to the second and fourth current terminals, and a sixth current terminal electrically connected to a first power supply.

Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

Abstract: An optical semiconductor module includes a resin body having a first surface and an opposed second surface, an optical device having a third surface and a fourth surface opposite the third surface, the optical device comprising an optical element located at the fourth surface, the optical element capable of at least one of receiving light from, and transmitting light through, the third surface, a first terminal located at the first surface of the resin body, and an electrical connection between the first terminal and the optical device, the electrical connection embedded in the resin body.