Patents by Inventor Hiroshi Uemura

Hiroshi Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608605
    Abstract: According to an embodiment, a circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first control terminal to receive a first input signal, a first current terminal to output an inverted output signal, and a second current terminal. The second transistor includes a second control terminal to receive a second input signal, a third current terminal to output a non-inverted output signal, and a fourth current terminal connected to the second current terminal. The third transistor includes a third control terminal to receive the inverted output signal, a fifth current terminal electrically connected to the second and fourth current terminals, and a sixth current terminal electrically connected to a first power supply.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Uemura
  • Patent number: 10429598
    Abstract: According to one embodiment, an optical device includes an optical element and a via. The optical element is provided directly on a second main surface opposed to a first main surface of a semiconductor substrate. The via is aligned with the optical element and formed to extend halfway in a thickness direction from the first main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
  • Publication number: 20190285814
    Abstract: According to one embodiment, the silicon substrate includes a thinned portion and a side wall provided around the thinned portion. The thinned portion is thinned selectively from one surface. The optical element is formed on a surface of the thinned portion. The surface of the thinned portion is opposite to the one surface of the silicon substrate. The light guide member includes a lens portion, a light guide portion, and an alignment portion. The light guide portion is provided between the lens portion and the optical element. The alignment portion is for an optical connector. The thinned portion of the silicon substrate is provided between the light guide portion of the light guide member and the optical element.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideto FURUYAMA, Yoichiro KURITA, Hiroshi UEMURA
  • Patent number: 10396060
    Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 27, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura
  • Publication number: 20190214952
    Abstract: According to an embodiment, a circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first control terminal to receive a first input signal, a first current terminal to output an inverted output signal, and a second current terminal. The second transistor includes a second control terminal to receive a second input signal, a third current terminal to output a non-inverted output signal, and a fourth current terminal connected to the second current terminal. The third transistor includes a third control terminal to receive the inverted output signal, a fifth current terminal electrically connected to the second and fourth current terminals, and a sixth current terminal electrically connected to a first power supply.
    Type: Application
    Filed: August 28, 2018
    Publication date: July 11, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi UEMURA
  • Publication number: 20190157252
    Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
    Type: Application
    Filed: February 23, 2018
    Publication date: May 23, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro KURITA, Hideto FURUYAMA, Hiroshi UEMURA
  • Patent number: 10203460
    Abstract: An optical semiconductor module includes a resin body having a first surface and an opposed second surface, an optical device having a third surface and a fourth surface opposite the third surface, the optical device comprising an optical element located at the fourth surface, the optical element capable of at least one of receiving light from, and transmitting light through, the third surface, a first terminal located at the first surface of the resin body, and an electrical connection between the first terminal and the optical device, the electrical connection embedded in the resin body.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Furuyama, Yoichiro Kurita, Hiroshi Uemura, Fumitaka Ishibashi
  • Publication number: 20180308831
    Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro KURITA, Hideto FURUYAMA, Hiroshi UEMURA, Fumitaka ISHIBASHI
  • Publication number: 20180275360
    Abstract: According to one embodiment, there is provided an optical coupling module including an optical device and an adaptor. The adaptor is attached to the optical device. The optical device has an optical element and a via. The optical element is placed on a first principal surface of a substrate. The via is placed in the substrate at a position corresponding to the optical element. The via has a first opening in a second principal surface of the substrate opposite to the first principal surface. The via does not reach the first principal surface. The adaptor has a guide hole having a second opening in a third principal surface of the adaptor opposite the second principal surface. The second opening corresponds to the first opening. The guide hole has a third opening in a fourth principal surface of the adaptor.
    Type: Application
    Filed: September 6, 2017
    Publication date: September 27, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi UEMURA, Hideto FURUYAMA, Yoichiro KURITA, Fumitaka ISHIBASHI
  • Patent number: 10032758
    Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: July 24, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
  • Publication number: 20180128998
    Abstract: An optical semiconductor module includes a resin body having a first surface and an opposed second surface, an optical device having a third surface and a fourth surface opposite the third surface, the optical device comprising an optical element located at the fourth surface, the optical element capable of at least one of receiving light from, and transmitting light through, the third surface, a first terminal located at the first surface of the resin body, and an electrical connection between the first terminal and the optical device, the electrical connection embedded in the resin body.
    Type: Application
    Filed: August 28, 2017
    Publication date: May 10, 2018
    Inventors: Hideto FURUYAMA, Yoichiro KURITA, Hiroshi UEMURA, Fumitaka ISHIBASHI
  • Patent number: 9776431
    Abstract: There are provided a medium conveying device and an image recording apparatus that can convey a medium without the generation of wrinkles and floating. Projections having the same size are regularly disposed on the peripheral surface of an image recording drum to form recessed portions and protruding portions on the peripheral surface of the image recording drum. An interval between the projections disposed in a middle region is set to be smaller than an interval between the projections disposed in both end regions. Accordingly, when a sheet is pressed against the peripheral surface of the image recording drum by a pressing roller, forces for pulling the sheet to the outside from the middle in a width direction can be generated. As a result, the sheet can be made to come into close contact with the peripheral surface of the image recording drum without the generation of wrinkles and floating.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 3, 2017
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshi Uemura
  • Publication number: 20170263595
    Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.
    Type: Application
    Filed: September 6, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
  • Patent number: 9749059
    Abstract: According to one embodiment, a current outputting circuit includes an output node, a first circuit outputting a first signal and a second signal based on an input signal, the first and second signals having phases of complementary relationship, and a second circuit outputting an output current from the output node based on the first and second signals. The second circuit includes a first current source with a first terminal and a second terminal, the first terminal being connected to a first power source, and a first transistor with a third terminal, a fourth terminal and a fifth terminal, the first signal being input to the third terminal, the fourth and fifth terminals sandwiching a first current path controlled by the first signal, the fourth terminal being connected to the second terminal, the fifth terminal being connected to the output node. The second signal is input to the fifth terminal.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 29, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Uemura
  • Patent number: 9729249
    Abstract: According to one embodiment, an amplification circuit includes an amplifier having a gain based on a gain control signal and amplifying an input signal by the gain, and a control portion outputting the gain control signal for increasing the gain after decreasing the gain based on an amplitude of the input signal, when the amplitude of the input signal is detected.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Uemura
  • Patent number: 9719942
    Abstract: Provided are a sintered ceramic and a ceramic sphere which are inhibited from suffering surface peeling due to fatigue resulting from repetitions of loading and can attain an improvement in dimensional accuracy when subjected to surface processing and which have excellent wear resistance and durability.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: August 1, 2017
    Assignees: NIKKATO CORPORATION, TSUBAKI NAKASHIMA CO., LTD.
    Inventors: Hiroshi Onishi, Hiroshi Ikeda, Hiroki Takimoto, Hiroshi Uemura, Kenji Yamada, Hideki Ono, Hiroyuki Matsuyama
  • Publication number: 20170207857
    Abstract: According to one embodiment, a current outputting circuit includes an output node, a first circuit outputting a first signal and a second signal based on an input signal, the first and second signals having phases of complementary relationship, and a second circuit outputting an output current from the output node based on the first and second signals. The second circuit includes a first current source with a first terminal and a second terminal, the first terminal being connected to a first power source, and a first transistor with a third terminal, a fourth terminal and a fifth terminal, the first signal being input to the third terminal, the fourth and fifth terminals sandwiching a first current path controlled by the first signal, the fourth terminal being connected to the second terminal, the fifth terminal being connected to the output node. The second signal is input to the fifth terminal.
    Type: Application
    Filed: March 10, 2016
    Publication date: July 20, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi UEMURA
  • Publication number: 20170151811
    Abstract: There are provided a medium conveying device and an image recording apparatus that can convey a medium without the generation of wrinkles and floating. Projections having the same size are regularly disposed on the peripheral surface of an image recording drum to form recessed portions and protruding portions on the peripheral surface of the image recording drum. An interval between the projections disposed in a middle region is set to be smaller than an interval between the projections disposed in both end regions. Accordingly, when a sheet is pressed against the peripheral surface of the image recording drum by a pressing roller, forces for pulling the sheet to the outside from the middle in a width direction can be generated. As a result, the sheet can be made to come into close contact with the peripheral surface of the image recording drum without the generation of wrinkles and floating.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Applicant: FUJIFILM Corporation
    Inventor: Hiroshi UEMURA
  • Publication number: 20170153401
    Abstract: According to one embodiment, an optical device includes an optical element and a via. The optical element is provided directly on a second main surface opposed to a first main surface of a semiconductor substrate. The via is aligned with the optical element and formed to extend halfway in a thickness direction from the first main surface of the semiconductor substrate.
    Type: Application
    Filed: September 14, 2016
    Publication date: June 1, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro KURITA, Hideto FURUYAMA, Hiroshi UEMURA, Fumitaka ISHIBASHI
  • Publication number: 20170054424
    Abstract: According to one embodiment, an amplification circuit includes an amplifier having a gain based on a gain control signal and amplifying an input signal by the gain, and a control portion outputting the gain control signal for increasing the gain after decreasing the gain based on an amplitude of the input signal, when the amplitude of the input signal is detected.
    Type: Application
    Filed: December 28, 2015
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi UEMURA