Patents by Inventor Hiroshi Umezaki

Hiroshi Umezaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8125734
    Abstract: Embodiments of the present invention provide a magnetic slider of which terminals have a sufficiently large process margin for the laser condition in the SBB process. According to one embodiment, a magnetic slider comprises: a read element and a write element; plural wiring lines which are connected to the read element and the write element; a protective film which covers the read element, the write element and the plural-wiring lines; plural slider pads formed on the protective film; and plural studs which respectively connect the slider pads and the wiring lines and are covered by the protective film, wherein each of the slider pads comprises a chromium film, a nickel iron film and a gold film, the nickel iron film is formed between the chromium film and the gold film, and the chromium film is formed between the nickel iron film and one of the studs and is in contact with the protective film.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 28, 2012
    Assignee: Hitachi Global Storage Technologies, Netherlands B.V.
    Inventors: Hiroshi Umezaki, Seiji Nakagawa, Yuhsuke Matsumoto, Yoshihisa Takeo, Gen Oikawa, Hiroshi Kamio
  • Patent number: 7929255
    Abstract: Embodiments of the present invention provide a magnetic head inspection system having a simple configuration capable of inspecting magnetic heads. According to one embodiment, the magnetic head inspection system comprises an inspection module which is provided with a magnetic disk where servo data including track identifier information are recorded, a spindle motor, a carriage having a mount structure to which a head assembly containing a magnetic head is secured, a voice coil motor and a main circuit section. An inspection circuit section instructs the main circuit section to execute control so as to move the magnetic head to a specific track and perform a certain read write operation by the magnetic head in order to inspect the magnetic head.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: April 19, 2011
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hiroshi Umezaki, Shinichi Iwasa
  • Patent number: 7518814
    Abstract: Embodiments of the invention provide an inexpensive magnetic head tester employing component parts of a production HDD and capable of exercising functions very close to those of a production HDD. In one embodiment, a magnetic head tester employs the VCM actuator and the control circuit of a production HDD and has a lightweight, simple HGA fixing mechanism mounted on an actuator arm. The HGA fixing mechanism fixes an HGA to the actuator arm by a method using a very light holding spring mounted on the arm, a method of mechanically clamping an HGA by using air pressure, or a method of fixing an HGA to the arm by elastically deforming a rubber clamping member by air pressure. Servo control is achieved by the actuator of a production VCM. An end part of the VCM actuator is stopped by a stopping mechanism and is held by a holding spring to prevent the runaway of the VCM actuator. Servo control is performed by balancing the driving force of the VCM and the resilience of the spring.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: April 14, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hiroshi Umezaki, Norifumi Miyamoto, Kazuhiko Washizu, Takehiko Hamaguchi, Kenji Itoh
  • Patent number: 7511981
    Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki
  • Publication number: 20080204913
    Abstract: Embodiments of the present invention provide a magnetic head inspection system having a simple configuration capable of inspecting magnetic heads. According to one embodiment, the magnetic head inspection system comprises an inspection module which is provided with a magnetic disk where servo data including track identifier information are recorded, a spindle motor, a carriage having a mount structure to which a head assembly containing a magnetic head is secured, a voice coil motor and a main circuit section. An inspection circuit section instructs the main circuit section to execute control so as to move the magnetic head to a specific track and perform a certain read write operation by the magnetic head in order to inspect the magnetic head.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Inventors: Hiroshi Umezaki, Shinichi Iwasa
  • Publication number: 20080094882
    Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Inventors: Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki
  • Patent number: 7349235
    Abstract: A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki, Hideo Asano, Koji Kitamura
  • Publication number: 20080062565
    Abstract: Embodiments of the present invention provide a magnetic slider of which terminals have a sufficiently large process margin for the laser condition in the SBB process. According to one embodiment, a magnetic slider comprises: a read element and a write element; plural wiring lines which are connected to the read element and the write element; a protective film which covers the read element, the write element and the plural-wiring lines; plural slider pads formed on the protective film; and plural studs which respectively connect the slider pads and the wiring lines and are covered by the protective film, wherein each of the slider pads comprises a chromium film, a nickel iron film and a gold film, the nickel iron film is formed between the chromium film and the gold film, and the chromium film is formed between the nickel iron film and one of the studs and is in contact with the protective film.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 13, 2008
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hiroshi Umezaki, Seiji Nakagawa, Yuhsuke Matsumoto, Yoshihisa Takeo, Gen Oikawa, Hiroshi Kamio
  • Publication number: 20070046286
    Abstract: Embodiments of the invention provide an inexpensive magnetic head tester employing component parts of a production HDD and capable of exercising functions very close to those of a production HDD. In one embodiment, a magnetic head tester employs the VCM actuator and the control circuit of a production HDD and has a lightweight, simple HGA fixing mechanism mounted on an actuator arm. The HGA fixing mechanism fixes an HGA to the actuator arm by a method using a very light holding spring mounted on the arm, a method of mechanically clamping an HGA by using air pressure, or a method of fixing an HGA to the arm by elastically deforming a rubber clamping member by air pressure. Servo control is achieved by the actuator of a production VCM. An end part of the VCM actuator is stopped by a stopping mechanism and is held by a holding spring to prevent the runaway of the VCM actuator. Servo control is performed by balancing the driving force of the VCM and the resilience of the spring.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 1, 2007
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hiroshi Umezaki, Norifumi Miyamoto, Kazuhiko Washizu, Takehiko Hamaguchi, Kenji Itoh
  • Patent number: 7123498
    Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: October 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki, Hideo Asano, Koji Kitamura
  • Publication number: 20060227600
    Abstract: A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction.
    Type: Application
    Filed: May 4, 2006
    Publication date: October 12, 2006
    Inventors: Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki, Hideo Asano, Koji Kitamura
  • Patent number: 6992924
    Abstract: The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current IB and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hisatada Miyatake, Hiroshi Umezaki, Kohji Kitamura, Toshio Sunaga, Kohki Noda, Hideo Asano
  • Publication number: 20050073897
    Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
    Type: Application
    Filed: October 12, 2004
    Publication date: April 7, 2005
    Inventors: Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki, Hideo Asano, Koji Kitamura
  • Patent number: 6826076
    Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki
  • Patent number: 6785154
    Abstract: A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki
  • Publication number: 20040090835
    Abstract: The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current In and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized.
    Type: Application
    Filed: October 7, 2003
    Publication date: May 13, 2004
    Inventors: Hisatada Miyatake, Hiroshi Umezaki, Kohji Kitamura, Toshio Sunaga, Kohki Noda, Hideo Asano
  • Patent number: 6639834
    Abstract: The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki
  • Publication number: 20020181275
    Abstract: The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.
    Type: Application
    Filed: April 26, 2002
    Publication date: December 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki
  • Publication number: 20020159286
    Abstract: A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 31, 2002
    Applicant: International Business Machines Corporation
    Inventors: Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki
  • Publication number: 20020136053
    Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
    Type: Application
    Filed: January 24, 2002
    Publication date: September 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Toshio Sunaga, Hiroshi Umezaki