Abstract: A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI.

Abstract: Time-axis data that include the peak waveform and the clock frequency of the power supply current when the LSI is switched are inputted to the LSI information input unit, and the LSI equivalent circuit creation unit creates an equivalent circuit of the LSI on the basis of the time-axis data. The time-axis/frequency-axis conversion unit converts the time-axis data to frequency-axis data. The equivalent circuit synthesis unit synthesizes the equivalent circuits of the printed wiring substrate, the power supply regulator, and the LSI to create a single equivalent circuit; the frequency-axis circuit analysis unit performs frequency-axis analysis of the single equivalent circuit; and the frequency-axis/time-axis conversion unit converts the results to time-axis data. The amount of fluctuation of the power supply voltage of an integrated circuit device can thereby be evaluated in a short time.

Abstract: Time-axis data that include the peak waveform and the clock frequency of the power supply current when the LSI is switched are inputted to the LSI information input unit, and the LSI equivalent circuit creation unit creates an equivalent circuit of the LSI on the basis of the time-axis data. The time-axis/frequency-axis conversion unit converts the time-axis data to frequency-axis data. The equivalent circuit synthesis unit synthesizes the equivalent circuits of the printed wiring substrate, the power supply regulator, and the LSI to create a single equivalent circuit; the frequency-axis circuit analysis unit performs frequency-axis analysis of the single equivalent circuit; and the frequency-axis/time-axis conversion unit converts the results to time-axis data. The amount of fluctuation of the power supply voltage of an integrated circuit device can thereby be evaluated in a short time.

Abstract: A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI.

Abstract: The present invention provides a method of forming a model for a circuit for simulating an electromagnetic interference, the model being described by a combination of at least one variable resistance and at least one load capacitance, wherein a variable resistance value of the at least one variable resistance and a load capacitance value of the at least one load capacitance are obtained based on at least one current flowing through at least one current path between at least one set of power terminals.

Abstract: A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.

Abstract: A design support system 100 according to the present invention comprises: an LSI library 10, in which rated characteristics of various LSIs are stored by an LSI library preparation unit 70; a decoupling capacitor library 20, in which rated characteristics of various capacitors are stored; a PCB library 30, in which the cross-sectional structures of various power wiring lines are stored; a decoupling capacitor search unit 40, for employing the LSI library 10 and the decoupling capacitor library 20; a power wiring determination unit 50, for employing the results obtained by the decoupling capacitor search unit 40, the LSI library 10 and the PCB library 30; and a design results output unit 60, for outputting the results received from the power wiring determination unit 50. Furthermore, the data in the three libraries can be updated or new data can be added.

Abstract: The present invention provides a method of forming a model for a circuit for simulating an electromagnetic interference, the model being described by a combination of at least one variable resistance and at least one load capacitance, wherein a variable resistance value of the at least one variable resistance and a load capacitance value of the at least one load capacitance are obtained based on at least one current flowing through at least one current path between at least one set of power terminals.

Abstract: The electromagnetic interference suppressing device of the present invention includes a plurality of connection layers and ground layers formed of a conductive material. The connection layers and the ground layers are alternately layered. Insulating layers, formed of an insulating material, intervene between the neighboring connection layers and ground layers. The odd connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end. The even connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end opposite to the odd connection-layered end. The bottommost connection layer is connected to a first signal terminal. The uppermost connection layer is connected to a second signal terminal. The ground layer is connected to a ground terminal.

Abstract: The present invention provides a power model for a semiconductor integrated circuit, wherein the power model comprises a logic gate circuit part representing an operating part of the semiconductor integrated circuit and an equivalent internal capacitive part representing a non-operating part of the semiconductor integrated circuit.

Abstract: A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.

Abstract: An output buffer of a semiconductor integrated circuit, including a P channel MOS transistor connected between first power source and an output terminal and a first N channel MOS transistor connected between a second power source and the output terminal, the first P and N channel MOS transistors being complementarily brought into a conductive state depending upon the level of an input signal given to the gates thereof for driving an output load including a signal transmission line connected with the output terminal is characterized in that each of said P and N channel MOS transistors has an output resistance equal to the characteristic impedance of the signal transmission line and in that said output buffer further includes an auxiliary control unit comprising a second N channel MOS transistor having an output resistance equal to the characteristic impedance of the signal transmission line connected in parallel with said first N channel MOS transistor between the second power source and the output terminal, a