Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9838389
    Abstract: An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 5, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20170341162
    Abstract: The present invention includes an end mill body which is formed of ceramic, a chip discharge flute which is formed on an outer periphery of the end mill body, a peripheral cutting edge which is formed on an intersection ridge line between a wall surface facing a tool rotation direction in the chip discharge flute and an outer peripheral surface of the end mill body, an end cutting edge which is formed on an intersection ridge line between the wall surface in the chip discharge flute and a tip surface of the end mill body, and a corner cutting edge which is positioned at a tip outer-peripheral part of the end mill body, connects an outer end of the end cutting edge and a tip of the peripheral cutting edge to each other, and has a convexly curved shape which is convex toward a tip outer-peripheral side of the end mill body.
    Type: Application
    Filed: February 24, 2016
    Publication date: November 30, 2017
    Inventors: Hiroshi Watanabe, Koutarou Sakaguchi
  • Publication number: 20170321780
    Abstract: [Problem] To provide a rotary damper wherein damping torque generated by rotation can be easily adjusted using a simple configuration. [Solution] A rotary damper 1 limits the movement of viscous fluid contained in a circular cylinder chamber 111, thereby generating damping torque against applied rotational force. This rotary damper 1 is configured such that: a lid 15 is screwed into a case 11; and the gap g1 between the lower surface 153 of the lid 15 and the upper surface 119 of a partition section 115 and the gap g2 between the lower surface 153 of the lid 15 and the upper surface 129 of a vane 122 can be adjusted by adjusting the amount of screwing of the lid 15 into the case 11. This means that adjusting the amount of movement of viscous fluid through the gaps g1, g2 can adjust damping torque generated by rotation.
    Type: Application
    Filed: November 6, 2015
    Publication date: November 9, 2017
    Inventors: Naohiro HORITA, Ryohei KANEKO, Hiroshi WATANABE, Wataru NISHIOKA
  • Publication number: 20170301437
    Abstract: In a manufacturing method for a thermistor element (3) including: a thermistor portion (49) which is a sintered body formed from a thermistor material; and a pair of electrode wires (25) which are embedded in the thermistor portion (49) and at least one end portion of each of the electrode wires projects at an outer side of the thermistor portion (49), the resistance value of the thermistor element (3) is adjusted by performing a removal processing of removing a part of the thermistor portion (49).
    Type: Application
    Filed: April 12, 2017
    Publication date: October 19, 2017
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Tomoki YAMAGUCHI, Shinji BAN, Hiroshi WATANABE, Yasuyuki OKIMURA, Hiroaki NAKANISHI, Seiji OYA, Seiya MATSUDA
  • Patent number: 9791482
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 17, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9790098
    Abstract: A sintered electroconductive oxide having a perovskite oxide type crystal structure represented by a compositional formula: M1aM2bMncAldCreOf wherein M1 represents at least one element selected from group 3 elements; and M2 represents at least one element selected from among Mg, Ca, Sr and Ba, wherein element M1 predominantly includes at least one element selected from Nd, Pr and Sm, and a, b, c, d, e and f satisfy the following relationships: 0.6005?a<1.000, 0<b?0.400, 0?c<0.150, 0.400?d<0.950, 0.050<e?0.600, 0.50<e/(c+e)?1.00, and 2.80?f?3.30. Also disclosed is a thermistor element including a thermistor portion which is formed of the sintered electroconductive oxide as well as a temperature sensor employing the thermistor element.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: October 17, 2017
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Hiroshi Watanabe, Shinji Ban, Tomoki Yamaguchi, Yasuyuki Okimura, Tomohiro Nishi
  • Publication number: 20170264388
    Abstract: A network management method executed by a processor included in a network managing device configured to manage a network in which a plurality of wavelength-multiplexed optical signals is transmitted, the method includes determining an active path and an auxiliary path for each of the plurality of optical signals; allocating, for each of links coupling adjacent nodes included in the network to each other, frequency bands to be used for the optical signals to the active paths for the optical signals so that frequency bands for the maximum rates of transmitting the optical signals do not overlap each other; and allocating, for each of the links, unallocated frequency bands within the frequency bands for the maximum transmission rates to the auxiliary paths for the optical signals.
    Type: Application
    Filed: February 1, 2017
    Publication date: September 14, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Watanabe, HIDEKI KAJITANI, Yusuke Kato, Hisatake Do, Hiroko Yokota, Hideyuki Sora
  • Publication number: 20170260933
    Abstract: A exhaust gas recirculation apparatus includes a throttle body; an intake manifold configured to distribute intake air to each intake port in an engine; an adapter member including a through channel capable of guiding the intake air to the intake manifold from the throttle body; and a gas supply path capable of guiding part of exhaust gas to an intake system from an exhaust system. The adapter member includes an inlet port, a discharge port, and a coupling channel. A first opening is wider than a second opening when the discharge port is divided into the first opening and the second opening at an imaginary plane, serving as a boundary, which includes a center line of a valve shaft and which extends along an extending-through direction of the through channel.
    Type: Application
    Filed: February 15, 2017
    Publication date: September 14, 2017
    Applicant: FUJI JUKOGYO KABUSHIKI KAISHA
    Inventor: Hiroshi WATANABE
  • Publication number: 20170240492
    Abstract: Synthesizing methanol from a synthesis gas and separating an unreacted gas from a reaction mixture obtained by passing through the synthesis step, the method including a synthesis loop having at least two synthesis steps and at least two separation steps; obtaining a first mixed gas by increasing through a circulator a pressure of a residual gas, obtained by removing a purge gas from the final unreacted gas separated from the final reaction mixture subsequent to the final synthesis step, and by mixing the residual gas with a fraction of a make-up gas; synthesizing methanol; separating a first unreacted gas from the first reaction mixture obtained in the synthesizing step; obtaining a second mixed gas by mixing the first unreacted gas and a fraction of the make-up gas; finally synthesizing methanol; and separating the final unreacted gas from the final reaction mixture obtained in the final synthesis step.
    Type: Application
    Filed: October 20, 2015
    Publication date: August 24, 2017
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yasuaki KAMBE, Kohei UCHIDA, Hiroshi WATANABE, Daigo HIRAKAWA, Tatsuya HASEGAWA
  • Publication number: 20170221916
    Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible to external of memory region is provided. The flash memory has sacrifice film formed on substrate. U-shaped groove is formed on sacrifice film, where multiple insulating film is laminated. Multiple insulating film includes silicon nitride film as charge storage layer. Low resistive material is disposed on multiple insulating film to form control gate. Select gate is formed on insulating film on side of control gate in self-aligned manner. Semiconductor regions opposite in conductivity to substrate on both sides of adjoining control gate and select gate to form source and drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with adjoining control gate and select gate between source and drain. In MOS-type transistor with control gate, threshold voltage is changeable according to injection/emission of charge to silicon nitride as charge storage layer, and thus work as non-volatile memory.
    Type: Application
    Filed: January 23, 2017
    Publication date: August 3, 2017
    Inventors: Te-Chang Tseng, Yukihiro Nagai, Riichiro Shirota, Hiroshi Watanabe
  • Publication number: 20170221998
    Abstract: An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/?s.
    Type: Application
    Filed: December 15, 2014
    Publication date: August 3, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei EBIHARA, Akihiro KOYAMA, Hidenori KOKETSU, Akemi NAGAE, Kotaro KAWAHARA, Hiroshi WATANABE, Kensuke TAGUCHI, Shiro HINO
  • Publication number: 20170221581
    Abstract: A semiconductor apparatus including a semiconductor chip is disclosed. The semiconductor chip includes a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses are randomly formed related to a part or a whole of the modular area of the modular region. The test circuit outputs a random number generated from physical properties intrinsic to the semiconductor chip according to a specification code received from a physical-chip-identification measuring device.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Inventor: Hiroshi Watanabe
  • Patent number: 9721742
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 1, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9705402
    Abstract: A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 11, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9698568
    Abstract: A cathode electrode, cathode pad electrodes, cathode wiring electrodes, an anode electrode, an anode pad electrode, and an anode wiring electrode are disposed on the surface of a vertical-cavity surface-emitting laser device. A light-emitting-region multilayer portion having active layers sandwiched by clad layers and DBR layers is formed directly below the anode electrode. A region where the light-emitting-region multilayer portion is formed serves as a light-emitting region. The light-emitting region is positioned closer to one end of the first direction than is a suction region onto which a flat collet sucks with respect to the first direction, in such a way that the light-emitting region is substantially in contact with or spaced a predetermined distance from the suction region.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: July 4, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiji Iwata, Ippei Matsubara, Takayuki Kona, Hiroshi Watanabe, Masashi Yanagase
  • Patent number: 9679652
    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 13, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20170162649
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Akihiko FURUKAWA, Shiro HINO, Hiroshi WATANABE, Masayuki IMAIZUMI
  • Publication number: 20170143701
    Abstract: Provided is a safe carbohydrate metabolism-ameliorating agent having an excellent carbohydrate metabolism-ameliorating action, and a safe GLP-1 secretion accelerator having an excellent GLP-1 secretion-accelerating action. The carbohydrate metabolism-ameliorating agent or GLP-1 secretion accelerator according to the present invention, which contains a specific cyclic dipeptide or a salt thereof as an active ingredient, is advantageous in that it has an excellent carbohydrate metabolism-ameliorating action, and that it is safe and can be ingested for a long period.
    Type: Application
    Filed: June 11, 2015
    Publication date: May 25, 2017
    Applicant: SUNTORY HOLDINGS LIMITED
    Inventors: Toshihide Suzuki, Kenji Yamamoto, Yoshinori Beppu, Hiroshi Watanabe
  • Patent number: 9650415
    Abstract: A uric acid-lowering agent containing, as an active ingredient, a tyrosine-containing cyclic dipeptide selected from the group consisting of cyclotryptophanyltyrosine, cycloseryltyrosine, cycloprolyltyrosine, cyclotyrosylglycine, cyclotyrosyltyrosine, cyclophenylalanyltyrosine, cycloleucyltyrosine, cyclolysyltyrosine, cyclohistidyltyrosine, cycloalanyltyrosine, cycloglutamyltyrosine, cyclovalyltyrosine, cycloisoleucyltyrosine, cyclothreonyltyrosine, cycloaspartyltyrosine, cycloasparaginyltyrosine, cycloglutaminyltyrosine, cycloarginyltyrosine, cyclomethionyltyrosine, and cyclotyrosylcysteine, or a salt thereof. The uric acid-lowering agent of the present invention has an excellent action of lowering a uric acid level, and the uric acid-lowering agent is useful in, for example, prevention or treatment of hyperuricemia, gout or the like.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: May 16, 2017
    Assignee: Suntory Holdings Limited
    Inventors: Toshihide Suzuki, Shinya Fukizawa, Yoshinori Beppu, Hiroshi Watanabe
  • Publication number: 20170129919
    Abstract: A cyclic dipeptide-containing composition containing each of tyrosine-containing cyclic dipeptides selected from the group consisting of cyclotryptophanyltyrosine, cycloseryltyrosine, cycloprolyltyrosine, cyclotyrosylglycine, cyclotyrosyltyrosine, cyclophenylalanyltyrosine, cycloleucyltyrosine, cyclolysyltyrosine, cyclohistidyltyrosine, cycloalanyltyrosine, cycloglutamyltyrosine, cyclovalyltyrosine, cycloisoleucyltyrosine, cyclothreonyltyrosine, cycloaspartyltyrosine, cycloasparaginyltyrosine, cycloglutaminyltyrosine, cycloarginyltyrosine, and cyclomethionyltyrosine, or a salt thereof in a specified amount. The cyclic dipeptide-containing composition of the present invention has an excellent action of lowering a uric acid level, and the cyclic dipeptide-containing composition is useful in, for example, prevention or treatment of hyperuricemia, gout or the like.
    Type: Application
    Filed: February 13, 2015
    Publication date: May 11, 2017
    Applicant: Suntory Holdings Limited
    Inventors: Toshihide Suzuki, Shinya Fukizawa, Yoshinori Beppu, Hiroshi Watanabe