Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180230095
    Abstract: The present invention provides a method for producing an atropisomer of a pyrrole derivative having excellent mineralocorticoid receptor antagonistic activity, and an intermediate thereof. A method for producing an atropisomer of a pyrrole derivative using a compound represented by (B) [wherein R1 represents a C1-C4 alkyl group, and R2 represents a 2-hydroxyethyl group or a carboxymethyl group] as a production intermediate.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Applicant: Daiichi Sankyo Company, Limited
    Inventors: Masashi Watanabe, Hiroshi Nagasawa, Noritada Sato
  • Publication number: 20180232539
    Abstract: A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
    Type: Application
    Filed: June 30, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, TAKESHI HAMAMOTO
  • Publication number: 20180234413
    Abstract: An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures P2P type communication on logical network, to physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 16, 2018
    Inventors: Hiroshi Watanabe, Takeshi Hamamoto
  • Publication number: 20180232360
    Abstract: A computer executes a process of: generating co-occurrence-message bunches by summarizing messages based on a relation in which the messages output from an apparatus are mutually output within a predetermined period; classifying the generated co-occurrence-message bunches into groups based on similarity among the co-occurrence-message bunches; determining a first message which is a representative of each of the groups based on an appearance characteristic of a word or a word string included in each message of each of the groups; determining a second message which is a representative of each of the co-occurrence-message bunches and is not repeated based on an appearance characteristic of a word or a word string included in each message in each co-occurrence-message bunch of each of the groups; and outputting the first message determined for the group including each co-occurrence-message bunch and the second message determined for each co-occurrence-message bunch in correlation with each co-occurrence-message b
    Type: Application
    Filed: February 6, 2018
    Publication date: August 16, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Asaoka, Ken Yokoyama, YUKIHIRO WATANABE, Hiroshi Otsuka, Reiko Kondo
  • Publication number: 20180231672
    Abstract: A radiation imaging apparatus comprises a sensor portion including a pixel array configured to acquire an image signal corresponding to radiation, and a plurality of detection elements arranged in the pixel array and configured to detect the radiation, and a readout circuit configured to read out the image signal from the sensor portion, wherein the readout circuit includes a signal processing circuit arranged to combine and process signals from the plurality of detection elements if determining the presence or absence of radiation irradiation, and to process a signal for each detection element or combine and process signals from a number of detection elements from among the plurality of detection elements, the number being less than the number of detection elements that include the plurality of detection elements, if determining a radiation dose.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventors: KEIGO YOKOYAMA, Minoru Watanabe, Masato Ofuji, Jun Kawanabe, Kentaro Fujiyoshi, Hiroshi Wayama
  • Publication number: 20180232270
    Abstract: A non-transitory computer-readable storage medium storing therein a failure analysis program that causes a computer to execute a process includes: extracting, for respective incidents, first material names that satisfy a first condition from character strings included in each incident; extracting, for the respective incidents, second material names, which are the same material names as the first material names, from the character strings included in each incident; calculating a combination of feature values corresponding respectively to the one or more features from character strings correlated with the extracted second material names, for the respective incidents and for the respective second material names; and specifying a specific combination that satisfies a second condition from the combinations of feature values corresponding to the respective material names, for the respective second material names.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 16, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Otsuka, Yukihiro Watanabe, Masahiro Asaoka, Reiko Kondo, Ken Yokoyama
  • Publication number: 20180233655
    Abstract: A piezoelectric material includes a metal oxide containing at least Ba, Ca, Ti, Zr, and Mn, in which the piezoelectric material has a perovskite structure, in which: x, which represents a ratio of a content (mol) of Ca to A (mol) representing a total content of Ba and Ca, falls within a range of 0.10x0.18; y, which represents a ratio of a content (mol) of Zr to B (mol) representing a total content of Ti, Zr, and Mn, falls within a range of 0.055?y?0.085; and z, which represents a ratio of a content (mol) of Mn to the B (mol), falls within a range of 0.003?z?0.012, and in which the piezoelectric material satisfies a relationship of 0?(|d31(31 20u)?d31(?20d)|)/|d31(?20u)|?0.08, and has a value of 130 pm/V or more for each of |d31(?20u)| and |d31(?20d)|.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 16, 2018
    Inventors: Hiroshi Saito, Akira Uebayashi, Tomohiro Watanabe, Yuto Niinuma, Yasushi Shimizu, Toshihiko Akatsuka
  • Patent number: 10049978
    Abstract: A semiconductor module includes a wiring substrate and two semiconductor devices mounted on the wiring substrate. The semiconductor module includes a housing having a rectangular frame body including four side walls. The housing includes a beam that bridges first side walls. A bus bar includes two end portions, upright portions each extending from one of the end portions in the thickness direction of an insulating substrate, bent portions each extending continuously with one of the upright portions, and an extension extending continuously with the bent portions. A section of the extension is embedded in the housing.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 14, 2018
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Naoki Kato, Shogo Mori, Harumitsu Sato, Hiroki Watanabe, Hiroshi Yuguchi, Koji Nishimura
  • Patent number: 10051765
    Abstract: To provide a shield film which is capable of suitably shielding electric field waves, magnetic field waves, and electromagnetic waves progressing from one side to the other side of the shield film and has good transmission characteristics, a shielded printed wiring board, and a method for manufacturing the shield film, a metal layer 3 which is 0.5 ?m to 12 ?m thick and an anisotropic conductive adhesive layer 4 which is anisotropic so as to be electrically conductive only in thickness directions are provided in a deposited manner, so that electric field waves, magnetic field waves, and electromagnetic waves progressing from one side to the other side of the shield film are suitably shielded.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 14, 2018
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Hiroshi Tajima, Sirou Yamauchi, Kenji Kamino, Masahiro Watanabe
  • Publication number: 20180227454
    Abstract: According to one embodiment, there is provided a terminal that includes a memory and a processor. The memory stores authentication-related information indicating that a first cloud completes approval of authentication, which is acquired by a terminal from the first cloud that transmits an instruction to perform a job to a job-performing apparatus of which registration is completed based on an instruction from the terminal, if the registration of the job-performing apparatus is completed. The processor retains the authentication-related information in a storage area if the job-performing apparatus is registered with the first cloud, and, if the authentication-related information is not present in the memory after the approval by the first cloud, acquires the authentication-related information from the storage area.
    Type: Application
    Filed: March 17, 2017
    Publication date: August 9, 2018
    Inventors: Takahiro Hagiwara, Hiroshi Watanabe, Akihiro Mizutani, Toshihiro Ida, Yusuke Hamada, Koji Endo, Kazuhiro Kamimura, Kazuhiro Ogura
  • Publication number: 20180222176
    Abstract: A movable member is gripped in a delamination-start configuration, and the other-end side of a rib of a delamination member is pressed towards the other-end side of a flexible plate. The flexible plate then warps and deforms about the other end side of the flexible plate, which is supported by a support member, the flexible plate deforming along the direction in which delamination progresses. In concert with the delamination action, a reinforcing plate also warps and deforms along with the flexible plate, the reinforcing plate being vacuum-chucked to an air-permeable electroconductive sheet on the flexible plate, and the reinforcing plate is sequentially delaminated from a substrate 2 along the direction in which delamination progresses.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 9, 2018
    Applicant: ASAHI GLASS COMPANY, LIMITED
    Inventors: Yasuaki Watanabe, Koji Nakamura, Tsubasa Kondo, Yasunori Ito, Yuki Hori, Hiroshi Utsugi
  • Patent number: 10042591
    Abstract: According to one embodiment, an image forming apparatus includes a processor, a network interface and a display device. The network interface under processor control acquires identification information of a different image forming apparatus on which a user is determined to have use authority based on user identification information of the user. The network interface under processor control also acquires an image forming job registered with the different image forming apparatus based on the acquired identification information of the different image forming apparatus. The display device under processor control displays the image forming job acquired by the network interface.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Takahiro Hagiwara, Shinji Makishima, Koji Endo, Hiroshi Watanabe, Akihiro Mizutani, Toshihiro Ida, Yusuke Hamada, Kazuhiro Ogura, Takeo Nishijima
  • Patent number: 10042686
    Abstract: A determination method, for determining a possibility of a new failure in a system, includes: obtaining first setting values for a plurality of setting items of the system when a failure in the system occurs; obtaining second setting values for the plurality of setting items when an input that the failure has been recovered is received; identifying at least one setting item from among the plurality of setting items based on the first setting values and the second setting values, the at least one setting item having a first setting value different from a second setting value; determining a value from among the first value and the second value of the at least one setting item; comparing an input value regarding the at least one setting item and the value; determining the possibility based on a result of the comparing; and outputting information regarding the possibility.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: August 7, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Otsuka, Yukihiro Watanabe, Yasuhide Matsumoto
  • Publication number: 20180219091
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: March 27, 2018
    Publication date: August 2, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20180215115
    Abstract: Technical problems of this invention is to create an injection molding device and an injection molding process for a test tube shaped preform, that can laminate a colored layer at certain positions of a wall of the reform with a certain thickness in a manner of a high degree of accuracy.
    Type: Application
    Filed: December 1, 2017
    Publication date: August 2, 2018
    Applicant: YOSHINO KOGYOSHO CO., LTD.
    Inventors: Hiroshi HOSOKOSHIYAMA, Junichi CHIBA, Yosuke WATANABE
  • Patent number: 10036302
    Abstract: A cooling device includes a first cooling medium circuit for circulating a cooling medium that passes through a main body of an engine to a first heat exchanger, a second cooling medium circuit for circulating a cooling medium that passes through the main body to a second heat exchanger, a control valve that is commonly used in the first and second cooling medium circuits, and a control device. The control valve includes a rotatable rotor, and is configured such that a rotation range of the rotor includes a water stop section in which the circuits are both closed. The control device restricts output power of the engine in a period in which the rotation angle is in the water stop section, when the rotor rotates via the water stop section at an operating time of the control valve.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 31, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroshi Watanabe
  • Publication number: 20180209076
    Abstract: One mode of the invention relates to a producing device for chopped fiber bundles comprising: cutting means including a cutting blade for cutting long fiber bundles, guide means for restricting the travel direction of the fiber bundles to be supplied to the cutting means, and widening means provided between the cutting means and the guide means and for widening the fiber bundles; and a producing method for chopped fiber bundles comprising: widening fiber bundles by widening means provided between a cutting means and guide means while restricting the travel direction of the long fiber bundles to be supplied to the cutting means by the guide means, and obtaining chopped fiber bundles by cutting the fiber bundles with the cutting means including a cutting blade.
    Type: Application
    Filed: March 20, 2018
    Publication date: July 26, 2018
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Tadao SAMEJIMA, Ryuichi ISHIKAWA, Hiroshi IWATA, Yukihiro MIZUTORI, Masatoshi KAMATA, Yasushi WATANABE, Hajime OKUTSU
  • Publication number: 20180208708
    Abstract: A rigid polyurethane resin composition contains a polyisocyanate component containing polyphenylmethane polyisocyanate and alicyclic polyisocyanate, and a polyol component. In the polyisocyanate component, the ratio of an isocyanate group derived from the alicyclic polyisocyanate with respect to the total amount of an isocyanate group derived from the polyphenylmethane polyisocyanate and the isocyanate group derived from the alicyclic polyisocyanate is 10 to 70 mol %.
    Type: Application
    Filed: July 15, 2016
    Publication date: July 26, 2018
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Hiroshi KANAYAMA, Minoru WATANABE, Makoto KAJIURA, Masakazu KAGEOKA, Satoshi YAMASAKI, Toshihiro TANAKA
  • Publication number: 20180212049
    Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Patent number: 10026644
    Abstract: Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: July 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe