Patents by Inventor Hiroshi Watanabe

Hiroshi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899402
    Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible externally of a memory region has a sacrifice film formed on a substrate. A U-shaped groove is formed on the sacrifice film, where multiple insulating films are laminated. The multiple insulating films includes a silicon nitride film as a charge storage layer. Low resistive material is disposed on the multiple insulating films to form a control gate. The select gate is formed on the insulating film on a side of the control gate in a self-aligned manner. Semiconductor regions opposite in conductivity to the substrate on both sides of the adjoining control gate and the select gate form a source and a drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with the adjoining control gate and the select gate between the source and the drain.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 20, 2018
    Assignee: IM Solution Co., Ltd.
    Inventors: Te-Chang Tseng, Yukihiro Nagai, Riichiro Shirota, Hiroshi Watanabe
  • Patent number: 9897089
    Abstract: A scroll compressor includes a pair of spiral plate bodies between which a compression chamber that compresses refrigerant is formed; a support configured to support one of the spiral plate bodies; a plurality of refrigerant paths extending through the support so as to provide communication between the compression chamber and an outside of the scroll compressor; and a plurality of check valves each of which is provided in the support for a corresponding one of the refrigerant paths, wherein each of the plurality of check valves includes a valve element and a valve chamber in which the valve element is accommodated, and at least one of the check valves is placed at a position away from a rest of the check valves in a rotation axis direction of the scroll compressor such that the valve chambers of the check valves do not interfere with each other.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 20, 2018
    Assignees: AISIN SEIKI KABUSHIKI KAISHA, SANDEN HOLDINGS CORPORATION
    Inventors: Yoshimi Watanabe, Shigeyuki Sunahara, Hiroshi Fujita, Ryosuke Miyazawa, Naoya Kogure, Tatsuki Nomura
  • Publication number: 20180046397
    Abstract: A method according to one embodiment includes instructing a first tape drive to load a parent tape medium, and instructing the first tape drive to retrieve identification (ID) information about the parent tape medium from metadata stored (saved) thereon. The first tape drive is instructed to write a first file part of a file to the parent tape medium. Information about the file and information about the first file part are written to the parent tape medium as metadata. A second tape drive is instructed to load and retrieve ID information about a child tape medium from metadata stored thereon. The second tape drive is instructed to write one or more subsequent file parts of the file to the child tape medium. The first tape drive is instructed to write the ID information about the child tape medium and attribute information about the one or more subsequent file parts stored to the child tape medium as metadata to the parent tape medium.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Terue Watanabe
  • Patent number: 9894095
    Abstract: A technology precluding attacks through peripheral devices thefts to a network of electronic appliance, by utilizing physical chip identification devices, is disclosed. The electronic appliance in the network are divided into the peripheral devices and stem servers managing registration information of the peripheral devices, wherein the stem servers serve as central control using software, and the peripheral devices are managed at device-level by having physical chip identification devices, thus the security of the whole network is efficiently reinforced.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 13, 2018
    Inventor: Hiroshi Watanabe
  • Patent number: 9886355
    Abstract: Rolling back data on tape in a file system is provided. A management tape is prepared. The management tape has only index files recorded thereon. The index files contain information about start positions and lengths of corresponding data files recorded on normal tapes. The index files further contain identification information for the normal tapes. A first index file of the management tape is read. The first index file is related to a data file to be rolled back. The first index file is read out from the management tape mounted on a first tape drive. The data file to be rolled back is read out of a first normal tape. The first normal tape is identified based on information in the first index file. The first normal tape is mounted on a second tape drive.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Hiroshi Itagaki, Setsuko Masuda, Tsuyoshi Miyamura, Terue Watanabe
  • Patent number: 9887224
    Abstract: A detection apparatus includes a plurality of conversion elements, an interlayer insulating layer, and a covering layer. Each of the plurality of conversion elements includes an electrode electrically connected to a corresponding one of a plurality of switching elements and a semiconductor layer disposed on the electrode. The interlayer insulating layer is disposed so as to cover the plurality of switching elements and composed of an organic material, and has a surface including a first region and a second region located outside the first region. The electrodes are disposed on the surface of the interlayer insulating layer in the first region. The covering layer is disposed on the surface of the interlayer insulating layer in the second region and composed of an inorganic material.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 6, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kentaro Fujiyoshi, Minoru Watanabe, Keigo Yokoyama, Masato Ofuji, Jun Kawanabe, Hiroshi Wayama
  • Patent number: 9887628
    Abstract: A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 6, 2018
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Hiroshi Watanabe, Brett E. Smith
  • Publication number: 20180028935
    Abstract: A solid-liquid separation device performs dehydration/deoiling from a mixture of water and/or oil and a solid. Substance A is capable of dissolving water and oil. The device includes substance B circulated while generating phase change in a closed system; a compressor; a first heat exchanger exchanging condensation heat of substance B and evaporation heat of substance A; a second heat exchanger exchanging evaporation heat of substance B and condensation heat of substance A; and a treatment tank for mixing substance A with an object to be treated; substance A having been evaporated while separated from the water or the oil in the first heat exchanger, and condensed in the second heat exchanger. The first heat exchanger is lower than the treatment tank in a vertical direction, and a connection port of the first heat exchanger and a lower portion of the treatment tank are connected with a flow path.
    Type: Application
    Filed: January 28, 2015
    Publication date: February 1, 2018
    Applicant: HITACHI, LTD.
    Inventors: Tadashi SANO, Hiroshi KUSUMOTO, Michiharu WATANABE, Mitsuhiro MATSUZAWA
  • Publication number: 20180034246
    Abstract: A spark plug 1 includes a cylindrical housing, a cylindrical insulator, a center electrode, a terminal bracket, a ground electrode, and a resistor. The insulator is held on the inside of the housing. The center electrode 4 is held on the inside of the insulator, with a tip end being projected therefrom. The terminal bracket is held on the inside of the insulator, with a base end part and being projected therefrom. The ground electrode forms a spark discharge gap G between itself and the center electrode. The resistor contains carbon and is disposed on the inside of the insulator so as to be located between the center electrode 4 and the terminal bracket. In an axial direction X of the spark plug, the resistor has a higher carbon content in a first region positioned on a tip side, compared to a second region positioned on a base end side.
    Type: Application
    Filed: February 10, 2016
    Publication date: February 1, 2018
    Inventors: Kenji HATTORI, Masamichi SHIBATA, Toshiya NAKAMURA, Yasuomi IMANAKA, Hirofumi SUZUKI, Hiroshi ARAKI, Tomoyuki WATANABE, Shin HASE
  • Patent number: 9877960
    Abstract: The present invention aims to provide antidementia agents which are free from the problem of side effects and are excellent in safety. The present invention also aims to provide agents for improving learning and memory which are useful for improvement of learning and memory and can be ingested continuously. The present invention provides antidementia agents and agents for improving learning and memory, each comprising a cyclic dipeptide with the 2,5-diketopiperazine structure as an active ingredient.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 30, 2018
    Assignees: SUNTORY HOLDINGS LIMITED, CEREBOS PACIFIC LIMITED
    Inventors: Nobuo Tsuruoka, Hiroshi Watanabe
  • Patent number: 9874808
    Abstract: The present invention provides a mask blank used to produce a halftone phase shift mask to which ArF excimer laser exposure light is to be applied. The present invention attains the object by providing the mask blank comprising a transparent substrate, and a light semitransmissive layer formed on the transparent substrate and made only of Si and N or a light semitransmissive layer formed on the transparent substrate and made only of Si, N and O, wherein the light semitransmissive layer has an extinction coefficient of 0.2 to 0.45 at a wavelength of ArF excimer laser exposure light, a refractive index of 2.3 to 2.7 at the wavelength of ArF excimer laser exposure light, and a transmittance of 15 to 38% at the wavelength of ArF excimer laser exposure light, and further has a layer thickness of 57 to 67 nm.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 23, 2018
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takashi Adachi, Youichi Miura, Hideyoshi Takamizawa, Katsuya Hayano, Youhei Ohkawa, Hiroshi Watanabe, Ayako Tani
  • Publication number: 20180019925
    Abstract: A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 18, 2018
    Inventor: Hiroshi Watanabe
  • Publication number: 20180019882
    Abstract: A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 18, 2018
    Inventor: Hiroshi Watanabe
  • Publication number: 20180013902
    Abstract: In accordance with an embodiment, the image forming apparatus comprises a display section, a connection section and a controller. The connection section connects with a device having a storage section. The controller detects connection and disconnection with the connection section and does not display a first screen displayed on the display section due to the connection with the device if the disconnection is detected.
    Type: Application
    Filed: March 14, 2017
    Publication date: January 11, 2018
    Inventors: Akihiro Mizutani, Hiroshi Watanabe, Toshihiro Ida, Kazuhiro Ogura, Takahiro Hagiwara, Kazuhiro Kamimura, Yusuke Hamada, Koji Endo
  • Publication number: 20170373152
    Abstract: The present techniques relate to a semiconductor device having resistance which has a positive temperature coefficient and a suitable value, and to a method for manufacturing a semiconductor device having resistance which has a positive temperature coefficient and a suitable value. The semiconductor device related to the present techniques is a bipolar device in which a current flows through a pn junction. The semiconductor device includes an n-type silicon carbide drift layer, a p-type first silicon carbide layer formed on the silicon carbide drift layer, and a p-type second silicon carbide layer formed on the first silicon carbide layer. Then, the second silicon carbide layer has a positive temperature coefficient of resistance.
    Type: Application
    Filed: August 5, 2015
    Publication date: December 28, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Hiroshi WATANABE
  • Patent number: 9838389
    Abstract: An integrated circuit, a code generating method, and a data exchange method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 5, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Hiroshi Watanabe
  • Publication number: 20170341162
    Abstract: The present invention includes an end mill body which is formed of ceramic, a chip discharge flute which is formed on an outer periphery of the end mill body, a peripheral cutting edge which is formed on an intersection ridge line between a wall surface facing a tool rotation direction in the chip discharge flute and an outer peripheral surface of the end mill body, an end cutting edge which is formed on an intersection ridge line between the wall surface in the chip discharge flute and a tip surface of the end mill body, and a corner cutting edge which is positioned at a tip outer-peripheral part of the end mill body, connects an outer end of the end cutting edge and a tip of the peripheral cutting edge to each other, and has a convexly curved shape which is convex toward a tip outer-peripheral side of the end mill body.
    Type: Application
    Filed: February 24, 2016
    Publication date: November 30, 2017
    Inventors: Hiroshi Watanabe, Koutarou Sakaguchi
  • Publication number: 20170321780
    Abstract: [Problem] To provide a rotary damper wherein damping torque generated by rotation can be easily adjusted using a simple configuration. [Solution] A rotary damper 1 limits the movement of viscous fluid contained in a circular cylinder chamber 111, thereby generating damping torque against applied rotational force. This rotary damper 1 is configured such that: a lid 15 is screwed into a case 11; and the gap g1 between the lower surface 153 of the lid 15 and the upper surface 119 of a partition section 115 and the gap g2 between the lower surface 153 of the lid 15 and the upper surface 129 of a vane 122 can be adjusted by adjusting the amount of screwing of the lid 15 into the case 11. This means that adjusting the amount of movement of viscous fluid through the gaps g1, g2 can adjust damping torque generated by rotation.
    Type: Application
    Filed: November 6, 2015
    Publication date: November 9, 2017
    Inventors: Naohiro HORITA, Ryohei KANEKO, Hiroshi WATANABE, Wataru NISHIOKA
  • Publication number: 20170301437
    Abstract: In a manufacturing method for a thermistor element (3) including: a thermistor portion (49) which is a sintered body formed from a thermistor material; and a pair of electrode wires (25) which are embedded in the thermistor portion (49) and at least one end portion of each of the electrode wires projects at an outer side of the thermistor portion (49), the resistance value of the thermistor element (3) is adjusted by performing a removal processing of removing a part of the thermistor portion (49).
    Type: Application
    Filed: April 12, 2017
    Publication date: October 19, 2017
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Tomoki YAMAGUCHI, Shinji BAN, Hiroshi WATANABE, Yasuyuki OKIMURA, Hiroaki NAKANISHI, Seiji OYA, Seiya MATSUDA
  • Patent number: 9791482
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 17, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe