Patents by Inventor Hiroshi Watase

Hiroshi Watase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11753823
    Abstract: A concrete structure includes a continuous fiber-reinforced polymer material arranged as a main reinforcing material or a tendon. A short fiber reinforcing material consisting of an organic fiber is mixed in 0.5% or more with respect to an entire volume. The continuous fiber-reinforced polymer material is shaped like a rod or a stranded wire. A ratio Lf/Gm between a fiber length Lf of the organic fiber of the short fiber reinforcing material and a maximum aggregate diameter Gm of a concrete composition is 1.2 to 3.7, and an aspect ratio Lf/De, in which De is an equivalent diameter that is a cross-sectional area of the organic fiber converted into a circle diameter, is 30 to 69.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 12, 2023
    Assignees: TOKYO ROPE MFG. CO., LTD., ORIENTAL SHIRAISHI CORPORATION
    Inventors: Yoshihiro Tanaka, Eiji Koda, Toru Tanaka, Meguru Tsunomoto, Hiroshi Watase, Tomohiro Ishii
  • Publication number: 20220145626
    Abstract: PROBLEM TO BE SOLVED: To provide a concrete structure and a concrete slab, which, by using a continuous fiber-reinforced polymer material as a main reinforcing material or a tendon, and by mixing a short fiber reinforcing material in concrete, compensate for the mechanical shortcomings of the continuous fiber-reinforced polymer material, not rusting, and taking advantage of superior characteristics of the continuous fiber-reinforced polymer material, with low manufacturing cost and ultra-high durability. MEANS TO SOLVE THE PROBLEM: In a concrete structure, in which a continuous fiber-reinforced polymer material is arranged as a main reinforcing material or a tendon, a short fiber reinforcing material consisting of an organic fiber is mixed in 0.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 12, 2022
    Applicants: TOKYO ROPE MGF. CO., LTD., ORIENTAL SHIRAISHI CORPORATION
    Inventors: Yoshihiro TANAKA, Eiji KODA, Toru TANAKA, Meguru TSUNOMOTO, Hiroshi WATASE, Tomohiro ISHII
  • Patent number: 11268280
    Abstract: In an anchorage (1) of continuous fiber-reinforced polymer (CFRP) strands that anchors continuous fiber-reinforced polymer strands (2) to concrete structures, there is provided an untwisted diameter-expanded portion (3) expanded to a diameter D2 by being radially expanded with respect to a diameter D1 of a general portion (4) of the CFRP strands (2) by untwisting any section of the CFRP strands (2) formed by stranding a plurality of element wires (20, 21) that are bundles of multiple continuous fibers, and filling and curing a time curable material (5) in a clearance among the element wires the untwisted section that is untwisted.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 8, 2022
    Assignees: TOKYO ROPE MANUFACTURING CO., LTD., ORIENTAL SHIRAISHI CORPORATION
    Inventors: Hiroshi Masuya, Yoshihiro Tanaka, Toru Tanaka, Eiji Koda, Hiroshi Watase, Meguru Tsunomoto
  • Publication number: 20210087815
    Abstract: In an anchorage 1 of continuous fiber-reinforced polymer (CFRP) strands that anchors continuous fiber-reinforced polymer strands 2 to concrete structures, there is provided an untwisted diameter-expanded portion 3 expanded to a diameter D2 by being radially expanded with respect to a diameter D1 of a general portion 4 of the CFRP strands 2 by untwisting any section of the CFRP strands 2 formed by stranding a plurality of element wires (20, 21) that are bundles of multiple continuous fibers, and filling and curing a time curable material 5 in a clearance among the element wires the untwisted section that is untwisted.
    Type: Application
    Filed: July 11, 2018
    Publication date: March 25, 2021
    Applicants: TOKYO ROPE MANUFACTURING CO., LTD., ORIENTAL SHIRAISHI CORPORATION
    Inventors: Hiroshi MASUYA, Yoshihiro TANAKA, Toru TANAKA, Eiji KODA, Hiroshi WATASE, Meguru TSUNOMOTO
  • Patent number: 8050085
    Abstract: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: November 1, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Masatoshi Takahashi, Takanori Yamazoe, Kozo Katayama, Toshihiro Tanaka, Yutaka Shinagawa, Hiroshi Watase, Takeo Kanai, Nobutaka Nagasaki
  • Publication number: 20090213649
    Abstract: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately.
    Type: Application
    Filed: August 29, 2002
    Publication date: August 27, 2009
    Inventors: Masatoshi Takahashi, Takanori Yamazoe, Kozo Katayama, Toshihiro Tanaka, Yutaka Shinagawa, Hiroshi Watase, Takeo Kanai, Nobutaka Nagasaki
  • Patent number: 7086087
    Abstract: It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: August 1, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masahiro Kaminaga, Takashi Endo, Masaru Ohki, Takashi Tsukamoto, Hiroshi Watase, Chiaki Terauchi, Kunihiko Nakada, Nobutaka Nagasaki, Satoshi Taira, Yuuichirou Nariyoshi, Yasuko Fukuzawa
  • Patent number: 6907526
    Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: June 14, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi
  • Publication number: 20010047480
    Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.
    Type: Application
    Filed: January 5, 2001
    Publication date: November 29, 2001
    Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi
  • Publication number: 20010016910
    Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.
    Type: Application
    Filed: January 5, 2001
    Publication date: August 23, 2001
    Inventors: Chiaki Tanimoto, Kunihiko Nakada, Takashi Tsukamoto, Shigeo Hirabayashi, Hiroshi Watase, Masatoshi Takahashi, Yuuichirou Nariyoshi