Abstract: A state acquisition unit (2020) acquires a state of a monitoring target in a captured image captured by a camera (3040). A monitoring point acquisition unit (2040) acquires, from a monitoring point information storage unit (3020), a monitoring point corresponding to the state of the monitoring target acquired by the state acquisition unit (2020). The monitoring point indicates a position to be monitored in the captured image. A presentation unit (2060) presents the monitoring point on the captured image.

Abstract: An information processing apparatus (2000) includes a first analyzing unit (2020), a second analyzing unit (2040), and an estimating unit (2060). The first analyzing unit (2020) calculates a flow of a crowd in a capturing range of a fixed camera (10) using a first surveillance image (12). The second analyzing unit (2040) calculates a distribution of an attribute of objects in a capturing range of a moving camera (20) using a second surveillance image (22). The estimating unit (2060) estimates an attribute distribution for a range that is not included in the capturing range of the moving camera (20).

Abstract: FET IC structures that enable formation of high-Q inductors in a “flipped” SOI IC structure made using a back-side access process, such as an single layer transfer (SLT) process. Essentially, the interconnect layer superstructure of an IC is split into two parts, a “lower” superstructure and an “upper” superstructure. In various embodiments, one or more low-resistance interconnect layers are fabricated within an upper superstructure formed after the application of a back-side access process, allowing fabrication of inductors in one or more low-resistance interconnect layer. A significant advantage of such IC structures is that the low-resistance interconnect layer or layers are relocated from being near the handle wafer of a conventional SLT IC to being spaced away from the handle wafer by intervening structures. Fabricating inductors in such spaced low-resistance interconnect layer or layers reduces electromagnetic coupling with the handle wafer and thus increases the Q factor of the inductors.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: A state acquisition unit (2020) acquires a state of a monitoring target in a captured image captured by a camera (3040). A monitoring point acquisition unit (2040) acquires, from a monitoring point information storage unit (3020), a monitoring point corresponding to the state of the monitoring target acquired by the state acquisition unit (2020). The monitoring point indicates a position to be monitored in the captured image. A presentation unit (2060) presents the monitoring point on the captured image.

Abstract: A state acquisition unit (2020) acquires a state of a monitoring target in a captured image captured by a camera (3040). A monitoring point acquisition unit (2040) acquires, from a monitoring point information storage unit (3020), a monitoring point corresponding to the state of the monitoring target acquired by the state acquisition unit (2020). The monitoring point indicates a position to be monitored in the captured image. A presentation unit (2060) presents the monitoring point on the captured image.

Abstract: A waterproof connector includes a contact, a housing, a seal member, and a cover member. An inserted portion of the housing is inserted in an insertion hole of a wall portion of a device case. The inserted portion includes an annular surface disposed flush to or with a step provided with respect to a surface of the wall portion. The seal member includes an annular first seal portion, fitted in an annular groove formed in the annular surface, and a covering portion, extending orthogonally from the first seal portion toward the surface side of the wall portion. The covering portion spanningly covers a first gap, which is a gap between an outer peripheral surface of the inserted portion and an inner peripheral surface of the insertion hole. The cover member is fixed to the wall portion across the covering portion.

Abstract: A state acquisition unit (2020) acquires a state of a monitoring target in a captured image captured by a camera (3040). A monitoring point acquisition unit (2040) acquires, from a monitoring point information storage unit (3020), a monitoring point corresponding to the state of the monitoring target acquired by the state acquisition unit (2020). The monitoring point indicates a position to be monitored in the captured image. A presentation unit (2060) presents the monitoring point on the captured image.

Abstract: Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconductor-on-insulator FET IC structures. Embodiments enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs. Embodiments include taking partially fabricated ICs made using a process which allows access to the back side of the FET, such as “single layer transfer” process, and then fabricating a conductive aligned supplemental (CAS) gate structure relative to the insulating layer juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the insulating layer. The IC structures present as a four or five terminal device: source S, drain D, primary gate G, CAS gate, and, optionally, a body contact.

Abstract: An information processing apparatus (2000) includes a first analyzing unit (2020), a second analyzing unit (2040), and an estimating unit (2060). The first analyzing unit (2020) calculates a flow of a crowd in a capturing range of a fixed camera (10) using a first surveillance image (12). The second analyzing unit (2040) calculates a distribution of an attribute of objects in a capturing range of a moving camera (20) using a second surveillance image (22). The estimating unit (2060) estimates an attribute distribution for a range that is not included in the capturing range of the moving camera (20).

Abstract: FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections.

Abstract: The present disclosure provides a wafer inspection device that can perform accurate inspection. The wafer inspection device includes a probe card having a plurality of contact probes formed to protrude toward a wafer W, a chuck top on which the wafer W is mounted and configured to move toward the probe card, and an aligner configured to adjust inclination of the chuck top relative to the probe card.

Abstract: The purpose of the present invention is to provide an orthodontic bracket on which a ligature member can be easily hooked, and is capable of preventing the ligature member from becoming detached and of reducing friction during movement of teeth. An orthodontic bracket (11) includes a plate-like base portion (12) disposed such that a back surface (15a) thereof opposes a tooth surface, a pair of projecting portions (21a, 21b) projecting in the thickness direction from a front surface (15b) side of the base portion (12) with a space between the projecting portions (21a, 21b) such that they form a groove-like slot (22) in which an arch wire (44) is accommodated, and a pair of wing portions (31a, 31b) projecting from the pair of projecting portions in outward directions. Hook grooves (36a, 36b) for inserting a ring (45) therein are formed between the back surfaces of the pair of wing portions and the upper surface of the base portion.

Abstract: Disclosed is a vehicle control apparatus applied to a vehicle including an automatic transmission. The vehicle control apparatus includes a friction brake apparatus for generating friction braking force acting on the vehicle, and a driving support ECU for performing cruise control. The driving support ECU causes the automatic transmission to perform downshift upon satisfaction of a downshift condition which is satisfied when a friction brake high load state continues for a predetermined determination threshold time.

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate.

Abstract: FET IC structures that enable formation of high-Q inductors in a “flipped” SOI IC structure made using a back-side access process, such as an single layer transfer (SLT) process. Essentially, the interconnect layer superstructure of an IC is split into two parts, a “lower” superstructure and an “upper” superstructure. In various embodiments, one or more low-resistance interconnect layers are fabricated within an upper superstructure formed after the application of a back-side access process, allowing fabrication of inductors in one or more low-resistance interconnect layer. A significant advantage of such IC structures is that the low-resistance interconnect layer or layers are relocated from being near the handle wafer of a conventional SLT IC to being spaced away from the handle wafer by intervening structures. Fabricating inductors in such spaced low-resistance interconnect layer or layers reduces electromagnetic coupling with the handle wafer and thus increases the Q factor of the inductors.

Abstract: An animal model (e.g., mouse) and method of use, and cell culture assay method, for characterizing or screening a test compound for its effect on late onset Alzheimer's disease (LOAD). The test compound may be used as a therapeutic agent for treatment of Alzheimer's disease (AD). The AD animal model may be haploinsufficient for Shugoshin 1 (Sgo1) gene, or may comprise a genetic modification enabling modulation of Sgo1 expression in the brain of the animal when exposed to an Sgo1 expression-modulating compound, such as tamoxifen. After the test compound is administered to the animal model, the presence or amount of an AD biomarker is assessed or measured.

Abstract: A waterproof connector includes a contact, a housing, a seal member, and a cover member. An inserted portion of the housing is inserted in an insertion hole of a wall portion of a device case. The inserted portion includes an annular surface disposed flush to or with a step provided with respect to a surface of the wall portion. The seal member includes an annular first seal portion, fitted in an annular groove formed in the annular surface, and a covering portion, extending orthogonally from the first seal portion toward the surface side of the wall portion. The covering portion spanningly covers a first gap, which is a gap between an outer peripheral surface of the inserted portion and an inner peripheral surface of the insertion hole. The cover member is fixed to the wall portion across the covering portion.

Abstract: An information processing apparatus (2000) includes a first analyzing unit (2020), a second analyzing unit (2040), and an estimating unit (2060). The first analyzing unit (2020) calculates a flow of a crowd in a capturing range of a fixed camera (10) using a first surveillance image (12). The second analyzing unit (2040) calculates a distribution of an attribute of objects in a capturing range of a moving camera (20) using a second surveillance image (22). The estimating unit (2060) estimates an attribute distribution for a range that is not included in the capturing range of the moving camera (20).