Abstract: A digital controlled oscillation circuit which has a wide oscillation frequency range and continuous and smooth transition of the oscillation frequency and can prevent occurrence of jitter: in which provision is made of a first delay circuit for delaying a first signal by a control signal and outputting the same as a first delay signal; a second delay circuit for delaying a second signal by the control signal and outputting the same as a second delay signal; an RS FF which switches a first output signal from low to high and switches a second output signal from high to low and outputs the same when receiving as its input the first delay signal, while switches the first output signal from high to low and switches the second output signal from low to high and outputs the same when receiving as its input the second delay circuit; and first and second switching detection circuits for generating first and second delay circuits when detecting that the first and second output signals switch from high to low.

Abstract: A clock control circuit 10 generates a reference clock signal CK.sub.2 in accordance with a clock signal CLK, performs a phase comparison with an oscillation signal S50 from a programmable mask generation circuit 50 at a phase comparator 20, generates an up signal S.sub.up or a down signal S.sub.dw in accordance with the result of comparison, and outputs the same to a counter 30. The counter 30 sequentially determines values of the bits from the most significant bit to the least significant bit, outputs the count S30 to a digital control delay line 40, and controls the frequency of an oscillation signal S40. After reaching the locked state, the counter 30 sequentially determines the values of bits from the least significant bit to the most significant bit in accordance with the up/down signal and tracks the reference clock signal CK.sub.2, therefore the lock up time of the digital PLL circuit can be shortened.

Abstract: A digital counter comprised of a synchronization judgement circuit and a counting circuit, the synchronization judging circuit receiving as an input signal the results of a comparison from a phase comparison circuit which compares the phase of a reference signal and an output signal of a frequency factoring circuit and outputting a phase synchronization judgement signal to the counting circuit, the counting circuit receiving as input the results of comparison and the phase synchronization judgement signal, performing a count based on the results of comparison, and successively determining a count from the most significant bit to the least significant bit. Also, a digital PLL circuit using the digital counter.

Abstract: A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.