Patents by Inventor Hiroshi Yao

Hiroshi Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8463986
    Abstract: A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: June 11, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Yamazaki, Yasuhiro Kimura, Hiroshi Yao
  • Patent number: 8266396
    Abstract: According to one embodiment, a free blocks included in a nonvolatile semiconductor memory are classified into a plurality of free block management lists. When a free block is acquired at normal priority, the free block is acquired from the free block management list in which a number of free blocks is larger than a first threshold. When a free block is acquired at high priority, the free block is acquired from the free block management list irrespective of the first threshold.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokuni Yano, Hiroshi Yao, Hajime Yamazaki, Tatsuya Sumiyoshi, Yoshimi Niisato, Takahiro Totsuka
  • Patent number: 8219767
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20120159051
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 21, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu HIDA, Hiroshi Yao, Norikazu Yoshida
  • Publication number: 20120079167
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Application
    Filed: March 2, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
  • Publication number: 20120072811
    Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.
    Type: Application
    Filed: February 25, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro FUKUTOMI, Hiroshi Yao, Shinichi Kanno, Shigehiro Asano, Toshikatsu Hida, Yasuhiro Kimura
  • Patent number: 8139453
    Abstract: When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the synchronous signal and the address information included in the sub data which was received simultaneously. There is provided a method for controlling the buffering of the main data which is reproduced from the optical disc, in which the main data and the sub data are received with taking word clocks which are partitioning timings having plural bits of the main data as a unit as references, a synchronous signal which is in synchronization with the main data is generated, and the buffering of the main data is started on the basis of the synchronous signal.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Shiro Shimizu, Naoyuki Kashii, Hiroshi Yao, Kiyokatsu Matsui
  • Publication number: 20110302361
    Abstract: A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided, thereby improving writing efficiency.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime YAMAZAKI, Yasuhiro Kimura, Hiroshi Yao
  • Publication number: 20110231610
    Abstract: According to one embodiment, a free blocks included in a nonvolatile semiconductor memory are classified into a plurality of free block management lists. When a free block is acquired at normal priority, the free block is acquired from the free block management list in which a number of free blocks is larger than a first threshold. When a free block is acquired at high priority, the free block is acquired from the free block management list irrespective of the first threshold.
    Type: Application
    Filed: September 17, 2010
    Publication date: September 22, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirokuni Yano, Hiroshi Yao, Hajime Yamazaki, Tatsuya Sumiyoshi, Yoshimi Niisato, Takahiro Totsuka
  • Publication number: 20110213913
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a managing unit, an order rule holding unit, a position information storing unit, a list selecting unit, a block selecting unit, a writing unit, and an updating unit. The managing unit holds for each of storage areas of the nonvolatile memory a free block list indicating free blocks. The order rule holding unit holds an order rule used to determine an order of the free block lists. The position information storing unit stores position information indicating the position of the free block list in the order rule. The list selecting unit selects the free block list corresponding to the position indicated by the position information and the block selecting unit selects the free block therefrom. The updating unit updates after the list selection the position information in the position information storing unit with position information indicating the position of the subsequently selected free block list.
    Type: Application
    Filed: September 15, 2010
    Publication date: September 1, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi YAO
  • Patent number: 8006272
    Abstract: According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Kambayashi, Tatsunori Kanai, Takeshi Saito, Hiroshi Yao, Shigeyasu Natsubori, Osamu Hori, Toshimitsu Kaneko, Toshihiro Morohoshi, Takahiro Harashima, Yoshinori Suzuki, Shigeru Oyanagi, Takeshi Aikawa
  • Patent number: 7971014
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Patent number: 7730249
    Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Tatsunori Kanai, Hiroshi Yao
  • Publication number: 20100027389
    Abstract: When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the synchronous signal and the address information included in the sub data which was received simultaneously. There is provided a method for controlling the buffering of the main data which is reproduced from the optical disc, in which the main data and the sub data are received with taking word clocks which are partitioning timings having plural bits of the main data as a unit as references, a synchronous signal which is in synchronization with the main data is generated, and the buffering of the main data is started on the basis of the synchronous signal.
    Type: Application
    Filed: September 7, 2007
    Publication date: February 4, 2010
    Inventors: Shiro Shimizu, Naoyuki Kashii, Hiroshi Yao, Kiyokatsu Matsui
  • Patent number: 7580610
    Abstract: A hierarchical memory scheme capable of improving a hit rate for the segment containing the random access point rather than improving the overall hit rate of the cache, and a data playback scheme capable of automatically detecting positions that are potentially used as playback start indexes by the user and attaching indexes, are disclosed. The hierarchical storage device stores random access point segment information from which a possibility for each segment to contain a point that can potentially be random accessed in future can be estimated, and controls a selection of the selected segments to be stored in the cache storage device according to the random access point segment information.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: August 25, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yao, Hirokuni Yano
  • Publication number: 20090172325
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Application
    Filed: August 26, 2008
    Publication date: July 2, 2009
    Inventors: Kenichiro YOSHII, Hiroshi YAO, Tomohide JOKAN, Tatsunori KANAI
  • Publication number: 20090164743
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Application
    Filed: August 27, 2008
    Publication date: June 25, 2009
    Inventors: Kenichiro YOSHII, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Patent number: 7458090
    Abstract: According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: November 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Kambayashi, Tatsunori Kanai, Takeshi Saito, Hiroshi Yao, Shigeyasu Natsubori, Osamu Hori, Toshimitsu Kaneko, Toshihiro Morohoshi, Takahiro Harashima, Yoshinori Suzuki, Shigeru Oyanagi, Takeshi Aikawa
  • Publication number: 20080244229
    Abstract: In an information processing apparatus, a fetch to a storage address of a first storage unit which stores a first instruction executed at first within a plurality of instructions that is included in a software and executed when a processor starts the software via the channel is detected. It is detected that the processor executed a specific instruction within the plurality of instructions via the channel. It is determined whether a predetermined time has passed since the detection of the fetch to the storage address until the detection of the execution of the specific instruction. When it is determined that the predetermined time has not passed, it is determined whether an interrupt to the processor is prohibited based on a result of the processor executing the specific instruction, and an access is released to the process according to a result of determination.
    Type: Application
    Filed: September 17, 2007
    Publication date: October 2, 2008
    Inventors: Hiroshi Yao, Kenichiro Yoshii, Tatsunori Kanai
  • Publication number: 20080178261
    Abstract: An information processing apparatus includes a storage unit, a processor, a channel, a detecting unit, and a control unit. The storage unit stores therein privilege software that is allowed to access a first access range. The processor executes the privilege software and software that is allowed to access a second access range. The channel connects the storage unit and the processor. The detecting unit detects a fetch request that is issued by the processor through the channel and specifies an address at which the privilege software is stored. The control unit controls an access range of the processor based on whether the fetch request is detected.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 24, 2008
    Inventors: Hiroshi Yao, Tatsunori Kanai, Kenichiro Yoshii