Patents by Inventor Hiroshi Yashiro

Hiroshi Yashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970162
    Abstract: Provided is a vehicle control device including: a recognizer that recognizes a surrounding situation of a vehicle, and identifies an interrupting vehicle trying to cut in a lane of the vehicle; a driving controller that controls steering and acceleration/deceleration of the vehicle without depending on an operation of the vehicle by a driver; and a mode determiner that determines a driving mode of the vehicle as one of a plurality of driving modes including a first driving mode and a second driving mode, wherein the second driving mode is a driving mode imposing a lighter task on the driver than the first driving mode, and a part of the plurality of driving modes including at least the second driving mode is controlled by the driving controller, and wherein the mode determiner restricts execution of the second driving mode when a relationship between the vehicle and the interrupting vehicle satisfies a predetermined condition.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 30, 2024
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Hiroshi Oguro, Katsuya Yashiro
  • Patent number: 11959677
    Abstract: A refrigeration apparatus includes: a refrigerant circuit through which refrigerant circulates; a controller to execute a plurality of refrigerant shortage sensing functions of sensing a shortage of an amount of the refrigerant; and an input device through which an operation mode to be set is input into the controller. The operation mode includes: a first mode in which energy-saving performance is emphasized; and a second mode in which the refrigeration apparatus is permitted to operate in a range in which reliability is ensured. In accordance with the operation mode set through the input device, the controller determines which one of sensing results obtained by the refrigerant shortage sensing functions is enabled and which one of sensing results obtained by the refrigerant shortage sensing functions is disabled. When a sensing result determined to be enabled shows a refrigerant shortage, the controller gives a notification about the refrigerant shortage.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 16, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanori Yashiro, Hiroshi Sata, Yusuke Arii
  • Patent number: 11255756
    Abstract: A testing vessel 1 includes a flexible vessel body 10 having a bottom and a hollow shape; and a partition 11 axially extending in the vessel body 10 and dividing an analyte extract containable space 50 in the vessel body 10 into two or more compartments. The testing vessel 1 enables two or more items to be readily tested with two or more test pieces.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: February 22, 2022
    Assignee: SEKISUI MEDICAL CO., LTD.
    Inventors: Kazunori Saito, Hiroyuki Oono, Kimiyoshi Nishitani, Motoki Morita, Shinji Matsuura, Hiroshi Yashiro
  • Publication number: 20190017903
    Abstract: A testing vessel 1 includes a flexible vessel body 10 having a bottom and a hollow shape; and a partition 11 axially extending in the vessel body 10 and dividing an analyte extract containable space 50 in the vessel body 10 into two or more compartments. The testing vessel 1 enables two or more items to be readily tested with two or more test pieces.
    Type: Application
    Filed: March 13, 2017
    Publication date: January 17, 2019
    Applicant: SEKISUI MEDICAL CO., LTD.
    Inventors: Kazunori SAITO, Hiroyuki OONO, Kimiyoshi NISHITANI, Motoki MORITA, Shinji MATSUURA, Hiroshi YASHIRO
  • Patent number: 7080227
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 7062627
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: June 13, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 6970912
    Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: November 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Takehisa Hayashi, Hiroshi Iwamoto, Kimitoshi Yamada
  • Publication number: 20040054865
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: August 19, 2003
    Publication date: March 18, 2004
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 6684312
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20030126420
    Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.
    Type: Application
    Filed: May 18, 1999
    Publication date: July 3, 2003
    Inventors: HIDEKI MURAYAMA, HIROSHI YASHIRO, SATOSHI YOSHIZAWA, KAZUO HORIKAWA, TAKEHISA HAYASHI, HIROSHI IWAMOTO, KIMITOSHI YAMADA
  • Patent number: 6557034
    Abstract: Before transferring data, a transmitting computer acquires a transfer rate of an I/O bus to which a communication control device in a receiving computer is connected. When transmitting data, the communication control device refers to a connection control table and a receiver control table, and chooses a transmitting queue for data transmission from a plurality of transmitting queues so that an interval is inserted between transmissions of data, and the data can be transmitted to the receiving computer without loss. The transmission intervals of data are determined based on the transfer rate of the I/O bus to which the communication control device in the receiving computer is connected.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: April 29, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hirofumi Fujita, Hideki Murayama, Hiroshi Yashiro
  • Patent number: 6477560
    Abstract: A control method of controlling a computer for controlling a resource connected to the computer and shared by a plurality of programs included in the computer includes the steps of storing a control information ID indicating a storage area in the main memory storing control information concerning access between a certain program and the resource in an OS space of a main memory, storing the control information ID in an adaptor connected to the main memory via a bus, and taking out the control information from the storage area included in the OS space, by using the control information ID stored in the adapter. In the case where the adapter runs short of a storage area, information that the adapter runs short of a storage area in the main memory is conveyed via the bus. By using the control information thus taken out, the resource is controlled.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Hiroshi Yashiro, Takehisa Hayashi, Masahiro Kitano
  • Publication number: 20020073292
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 13, 2002
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20020029325
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: January 8, 1999
    Publication date: March 7, 2002
    Inventors: HIDEKI MURAYAMA, KAZUO HORIKAWA, HIROSHI YASHIRO, MASAHIKO YAMAUCHI, YASUHIRO ISHII, DAISUKE SASAKI
  • Patent number: 6108694
    Abstract: A memory disc sharing method in which a plurality of computers share a memory disc through a network, wherein a command in accordance with which the memory disc is accessed is received by a network interface apparatus, and when a requested computer to which a request of the command has been made is any of other computers, the command is transmitted to the any of other computers, and when the requested computer is a computer concerned, the command is stored in a memory disc command queue. The network interface apparatus retrieves the command from the memory disc command queue, and executes the processing of reading out/writing data from/to the memory disc in the computer concerned when a requesting computer from which a request of the command has been made is the computer concerned, and carries out the data transfer between the memory disc in the computer concerned and the requesting computer when the requesting computer is any of other computers.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yashiro, Hideki Murayama, Hirofumi Fujita, Takehisa Hayashi, Masahiro Kitano
  • Patent number: 5935205
    Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: August 10, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Takehisa Hayashi, Hiroshi Iwamoto, Kimitoshi Yamada
  • Patent number: 5649102
    Abstract: A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer.
    Type: Grant
    Filed: November 25, 1994
    Date of Patent: July 15, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Yamauchi, Satoshi Yoshizawa, Hideki Murayama, Takehisa Hayashi, Akira Kito, Hiroshi Yashiro, Tsutomu Goto, Kimitoshi Yamada, Toru Horimoto