Patents by Inventor Hiroshi Yoneda

Hiroshi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6067066
    Abstract: A voltage output circuit has decoders, a selecting circuit, a logical circuit and an output circuit in order to select one of plural gradation power source lines for a prescribed period based upon k bits and m bits of an n-bit digital signal. The k bits of the digital signal are converting into 2.sup.k decoded signals by one decoder, and another m bits are converted into 2.sup.m decoded signals by the other decoder. The selecting circuit generates a signal for selecting one of periods which were obtained by dividing one horizontal scanning period into 2.sup.k based upon k-numbered timing signals by using the 2.sup.k decoded signals. The logical circuit generates 2.sup.n signals composed of combinations of the signals from the selecting circuit and the 2.sup.m decoded signals. Moreover, one of the 2.sup.m gradation power source lines is selected by an output switch by using the signal from the logical circuit.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: May 23, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Osamu Sasaki, Hiroshi Yoneda
  • Patent number: 6064364
    Abstract: An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n.times.m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: May 16, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Yasushi Kubota, Hiroshi Yoneda, Tamotsu Sakai
  • Patent number: 6054976
    Abstract: An image display device includes an operational amplifier, a signal amplifier provided with a condenser for setting a gain of the operational amplifier, a signal amplifier circuit having such signal amplifier or a buffer amplifier, the signal amplifier circuit being provided with an offset adjusting function, and a data signal line drive circuit having a signal amplifier or a signal line drive circuit. The described arrangement enables the gain of the signal amplifier to be set by a capacitance of the condenser, thereby providing a signal amplifier circuit which permits the gain to be set much more precisely as compared to the conventional signal amplifier circuits even when adopting a signal amplifier formed on a semiconductor thin film such as a polycrystalline silicone thin film. The arrangement also provides a signal amplifier circuit which permits a voltage in the same level as a voltage of the input signal to be outputted.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: April 25, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Kenichi Katoh, Hiroshi Yoneda
  • Patent number: 5936596
    Abstract: An image-displaying apparatus that is provided with a display section which is constituted of a plurality of pixels disposed in the form of a matrix and which is capable of displaying images that are different depending on viewing angles from which they are viewed. This arrangement makes it possible to select desired images by changing the viewing angles from which the display section is viewed. This eliminates the necessity of having to wear conventional glasses with a shutter and their inherent inconveniences. Further, this apparatus is suitable for public use as well as for private use, even when only one apparatus is used.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: August 10, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeto Yoshida, Hiroshi Yoneda, Minehiro Konya
  • Patent number: 5926234
    Abstract: Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: July 20, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Yasushi Kubota, Hiroshi Yoneda
  • Patent number: 5926156
    Abstract: A driving circuit in a matrix type image display apparatus including a plurality of groups each including four standard unit circuits and one backup unit circuit. Each standard unit circuit includes disconnecting means for isolating the standard unit circuit from the driving circuit, and the backup unit circuit includes connecting means for connecting the backup unit circuit to an input signal line and an output signal line of any of the standard unit circuits within a group. The number of the backup unit circuits can be changed in accordance with a conforming ratio of each unit circuit, which makes it possible to eliminate idle backup unit circuits while maintaining a high overall conforming ratio of the driving circuit, thereby enhancing manufacturing efficiencies and reducing manufacturing costs.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: July 20, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Yasushi Kubota, Hiroshi Yoneda, Osamu Sasaki, Ichiro Shiraki
  • Patent number: 5926158
    Abstract: An active matrix type image display apparatus which includes: a plurality of data signal lines; a plurality of scanning signal lines crossing the plurality of data signal lines; and a plurality of pixel portions disposed in a matrix in areas enclosed by the plurality of data signal lines and the plurality of scanning signal lines, wherein each of the plurality of pixel portions includes: a pixel capacitor for storing electric charge supplied from at least one of the plurality of data signal lines, to display an image; storage unit connected to the pixel capacitor; and switching unit which alternately selects one of an operation for electrically connecting the pixel capacitor to the storage unit and an operation for electrically disconnecting the pixel capacitor from the storage unit.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: July 20, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Yoneda, Kenichi Katoh, Yutaka Ishii, Yasushi Kubota
  • Patent number: 5898322
    Abstract: A logic circuit performs a logic operation on a plurality of input logic signals and outputting a resultant logic signal. The logic circuit comprises a pass-transistor logic circuit including: a plurality of field effect transistors, at least two of the plurality of field effect transistors being coupled in series, a gate electrode of each of the at least two field effect transistors receiving a corresponding first logic signal, and one of drain and source electrodes ditto receiving a corresponding second logic signal; and a node for coupling the other of the drain and source electrodes of the at least two field effect transistors, and for outputting the resultant logic signal. The plurality of field effect transistors are thin film transistors (TFTs).
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: April 27, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Hiroshi Yoneda
  • Patent number: 5844538
    Abstract: An image display apparatus can be arranged so that a picture element capacity obtains a value provides display data retention of less than 99% by writing same data to a picture element a plurality of times during 1 frame period. This makes it possible to disuse the auxiliary capacity and to improve an aperture ratio. Moreover, with the present invention, an MOS transistor arranged in each picture element as a switching element for driving the picture element, a scan signal line driving circuit and a data signal line driving circuit for transmitting a driving signal based upon display data to the MOS transistor through a data signal line and a scan signal line, and a first frame memory and a second frame memory provided outside the picture element for storing display data to be outputted to a data signal line driving circuit for 1 frame are formed on one substrate. As a result, it is possible to improve package efficiency and lower cost by using a driver monolithic technique.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 1, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Manabu Matsuura, Yasushi Kubota, Hiroshi Yoneda, Yoshitaka Yamamoto
  • Patent number: 5835170
    Abstract: An active matrix type liquid crystal display device includes: a plurality of data lines and a plurality of gate lines disposed in a lattice manner; and a pixel having a pixel transistor, a pixel electrode, and a storage capacitor, the pixel being disposed at a intersection between the data line and the gate line. The storage capacitor includes electrodes connected to the pixel electrode and electrodes connected to a plurality of gate lines, none of which is a gate line for driving the pixel.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 10, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Fujiwara, Hiroshi Yoneda
  • Patent number: 5790213
    Abstract: A liquid crystal display device includes pixels, arranged in a two-dimensional matrix on a substrate, for displaying an image, and several types of transistors, fabricated monolithically on the substrate for driving the respective pixels. One transistor in each pixel is juxtaposed on a periphery section of an adjacent pixel. By sharing such sections between adjacent pixels the fabrication of the transistors is simplified with the area occupied by each transistor and the pixel size reduced.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: August 4, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Osamu Sasaki, Ichiro Shiraki, Manabu Matsuura, Hiroshi Yoneda
  • Patent number: 5777591
    Abstract: A matrix display apparatus includes a matrix of pixels divided into a plurality of groups of pixels and data signal lines for delivering a data signal to a pixel. The data signal lines are distributed along the direction of a column. The apparatus also includes scanning signal lines for applying a scanning signal to a pixel, the scanning signal lines being distributed along the direction of a row. The apparatus also includes a first switch, disposed from each of the plurality of pixels, for allowing the data signal to be applied to the corresponding pixel based on the scanning signal. The apparatus also includes a second switch, disposed for each of the pixels in at least one of the plurality of the pixel groups, for controlling a timing for allowing the data signal to be applied to the corresponding pixel. The second switch is connected in series to the first switch between the first switch and the data signal line.
    Type: Grant
    Filed: May 5, 1994
    Date of Patent: July 7, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Hiroshi Yoneda
  • Patent number: 5748165
    Abstract: In order to sufficiently save the power consumption and to lower the withstand voltage of elements, by having one data signal line per one row of pixels and one scanning signal line per one line of pixels, the polarity of data written in the data signal line is varied each one field period. The power source magnitude of the scanning signal lines to be written is further varied each one field period. Specifically, on opposing sides of the pixel array, data signal line driving circuits are provided. The data signal line driving circuits supply voltages of different magnitude and polarity. Adjoining pairs of data signal lines are connected to each of the data signal line driving circuits with analog switches. In a certain display period, such as every field period, the analog switches each select one of a pair of adjacent data signal lines. In the next display period, the reverse selection is made.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: May 5, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Hiroshi Yoneda, Kenichi Katoh
  • Patent number: 5734366
    Abstract: An image display device includes an operational amplifier, a signal amplifier provided with a condenser for setting a gain of the operational amplifier, a signal amplifier circuit having such signal amplifier or a buffer amplifier, the signal amplifier circuit being provided with an offset adjusting function, and a data signal line drive circuit having a signal amplifier or a signal line drive circuit. The described arrangement enables the gain of the signal amplifier to be set by a capacitance of the condenser, thereby providing a signal amplifier circuit which permits the gain to be set much more precisely as compared to the conventional signal amplifier circuits even when adopting a signal amplifier formed on a semiconductor thin film such as a polycrystalline silicone thin film. The arrangement also provides a signal amplifier circuit which permits a voltage in the same level as a voltage of the input signal to be outputted.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: March 31, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Kenichi Katoh, Hiroshi Yoneda
  • Patent number: 5712653
    Abstract: An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n.times.m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: January 27, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Yasushi Kubota, Hiroshi Yoneda, Tamotsu Sakai
  • Patent number: 5708454
    Abstract: A matrix type display apparatus includes pixel electrodes arranged in a matrix, data signal lines and scanning signal lines for driving the pixel electrodes, and a data signal line driving circuit. The data signal line driving circuit includes sampling capacitors for keeping sampled data obtained by sequentially sampling image data over one horizontal scanning period, holding capacitors for holding the sampled data transmitted from the sampling capacitors upon termination of the horizontal scanning period and then outputting the sampled data to data signal lines, and a precharging circuit for precharging the corresponding holding capacitors by applying a predetermined voltage to the holding capacitors before the sampled data is transmitted to the holding capacitors.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: January 13, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Hiroshi Yoneda
  • Patent number: 5677744
    Abstract: The display apparatus of the invention includes: a first substrate and a second substrate which are disposed so as to face each other; a display medium having variable optical characteristics sandwiched between the first substrate and the second substrate; a display circuit provided on the first substrate; and a coordinate input section for inputting coordinates of a point on the first substrate.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: October 14, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Yoneda, Hiroshi Tsujioka, Takao Tagawa
  • Patent number: 5671026
    Abstract: Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: September 23, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Yasushi Kubota, Hiroshi Yoneda
  • Patent number: 5654506
    Abstract: A heat type air flow meter with improved resistance to radio wave interference by restraining a high frequency noise from a resistor and the supporting materials thereof provided in air passage. At least one high frequency band cut-off filter having a capacitor and a inductor is provided between, on one hand, a heating resistor and a heat sensitive resistor and, on the other hand, a temperature control circuit, and an intermediate connecting point of one end of the capacitor connected with one end of the inductor is also connected to both resistors. Thereby, as the resistivity to the radio wave interference is effectively improved cost reduction and compactness of the flow meter can be achieved.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignees: Hitachi, Ltd., Hitachi Automotive Engineering Co., Ltd.
    Inventors: Hiroshi Yoneda, Masuo Akamatsu
  • Patent number: 5610414
    Abstract: In a semiconductor device wherein an active device circuit and electrically conductive lines, such as a power source line for supplying power to the semiconductor active device circuit or signal lines for inputting a signal to the semiconductor active device circuit, are formed together on a single substrate, an improved arrangement wherein a conventional power source or signal line is formed by using a plurally of individual lines of substantially uniform electrical resistance where the electrical resistance of each line is limited to a predetermined value. Moreover, a waveform deterioration response signal component is added to a signal transmitted through the signal lines so as to improve the transmitted signal by compensating for waveform deterioration experienced during circuit operation. In addition, an electrical capacity forming electrode is provided alongside substantial length of the power source line.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: March 11, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Yoneda, Shigeto Yoshida, Kenichi Katoh, Yasukuni Yamane, Yutaka Ishii