Patents by Inventor Hiroshige Abe

Hiroshige Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 8238440
    Abstract: The present invention is directed to lessen burden at the time of solving a conflict of overlapping processes in processes for a plurality of interruption factors. On completion of data transfer to an external memory, a data transfer completion interruption of high priority is generated. In the case where data transfer of predetermined number of packets is not completed in reception interruption, a timer interruption of low priority is generated. Before processing data in an external memory responding to the interruption, the number of transfer packets is obtained from a counter. After restart of reception, the counter stores the number of transfer restart packets. After obtaining the number of transfer packets from a counter responding to the occurrence of the timer interruption, a data transfer completion interruption is generated.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshige Abe, Isamu Mochizuki, Mika Mizutani
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20100303157
    Abstract: The present invention is directed to lessen burden at the time of solving a conflict of overlapping processes in processes for a plurality of interruption factors. On completion of data transfer to an external memory, a data transfer completion interruption of high priority is generated. In the case where data transfer of predetermined number of packets is not completed in reception interruption, a timer interruption of low priority is generated. Before processing data in an external memory responding to the interruption, the number of transfer packets is obtained from a counter. After restart of reception, the counter stores the number of transfer restart packets. After obtaining the number of transfer packets from a counter responding to the occurrence of the timer interruption, a data transfer completion interruption is generated.
    Type: Application
    Filed: May 19, 2010
    Publication date: December 2, 2010
    Inventors: Hiroshige Abe, Isamu Mochizuki, Mika Mizutani