Patents by Inventor Hiroshige Kogayu

Hiroshige Kogayu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7632744
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Patent number: 7629669
    Abstract: A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: December 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Koji Ishikawa, Kazutaka Mori, Hiroshige Kogayu, Tamotsu Miyake, Mitsugu Kusunoki
  • Patent number: 7522083
    Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: April 21, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Ryusuke Sahara, Mitsugu Kusunoki, Kazutaka Mori, Hiroshige Kogayu
  • Publication number: 20080227251
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Application
    Filed: April 14, 2008
    Publication date: September 18, 2008
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Patent number: 7375013
    Abstract: Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: May 20, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Publication number: 20080055140
    Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
    Type: Application
    Filed: October 23, 2007
    Publication date: March 6, 2008
    Inventors: Ryusuke SAHARA, Mitsugu Kusunoki, Kazutaka Mori, Hiroshige Kogayu
  • Patent number: 7310266
    Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 18, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Ryusuke Sahara, Mitsugu Kusunoki, Kazutaka Mori, Hiroshige Kogayu
  • Patent number: 7253465
    Abstract: In a dual polymetal gate electrode, the contact resistance at the interface of silicon films increases due to mutual-diffusion of impurities of p-type and n-type silicon films through a refractory metal and metal nitride deposited thereon. A way of inhibiting the phenomenon is carbon implantation into a refractory metal and refractory metal nitride on the boundary of p-type silicon and n-type silicon, cutting the path, or isolating it by an insulator. Thereby, mutual-diffusion of impurities through a refractory metallic film and nitride film of refractory metal is inhibited, resulting in an increase in the contact resistance of metal nitride film and silicon film and a decrease in the deviation of threshold voltage of the MISFET.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Yamamoto, Yoshitaka Tadaki, Hiroshige Kogayu
  • Publication number: 20060244103
    Abstract: A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 2, 2006
    Inventors: Koji Ishikawa, Kazutaka Mori, Hiroshige Kogayu, Tamotsu Miyake, Mitsugu Kusunoki
  • Publication number: 20060245266
    Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 2, 2006
    Inventors: Ryusuke Sahara, Mitsugu Kusunoki, Kazutaka Mori, Hiroshige Kogayu
  • Publication number: 20060175651
    Abstract: Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Application
    Filed: April 3, 2006
    Publication date: August 10, 2006
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Patent number: 7053459
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: May 30, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Publication number: 20040211999
    Abstract: In a dual polymetal gate electrode, the contact resistance at the interface of silicon films increases due to mutual-diffusion of impurities of p-type and n-type silicon films through a refractory metal and metal nitride deposited thereon. A way of inhibiting the phenomenon is carbon implantation into a refractory metal and refractory metal nitride on the boundary of p-type silicon and n-type silicon, cutting the path, or isolating it by an insulator. Thereby, mutual-diffusion of impurities through a refractory metallic film and nitride film of refractory metal is inhibited, resulting in an increase in the contact resistance of metal nitride film and silicon film and a decrease in the deviation of threshold voltage of the MISFET.
    Type: Application
    Filed: April 5, 2004
    Publication date: October 28, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Naoki Yamamoto, Yoshitaka Tadaki, Hiroshige Kogayu
  • Publication number: 20040051153
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Application
    Filed: August 20, 2003
    Publication date: March 18, 2004
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida