Patents by Inventor Hiroshisa Tanabe

Hiroshisa Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090015299
    Abstract: A reference voltage is applied from a reference voltage generating circuit to the non-inverting input terminal of an amplifier for supplying a drive voltage to the gate terminal of an NMOS transistor, and the output voltage appearing at the source terminal of the NMOS transistor is divided by a resistor pair and applied to the inverting input terminal of the amplifier. The voltage obtained by adding a voltage equal to or higher than the voltage for sufficiently driving the NMOS transistor to the output voltage appearing at the source terminal of the NMOS transistor is generated by a charge pump circuit and supplied to the amplifier as a power supply voltage. With this configuration, the drive voltage for the NMOS transistor is suppressed to the required minimum voltage while the drive voltage is obtained securely. The power consumption in the amplifier can thus be suppressed.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takashi RYU, Takuya Ishii, Naoyuki Nakamura, Hiroshisa Tanabe