Patents by Inventor Hirosi Oodaira

Hirosi Oodaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4997791
    Abstract: An IC card comprises a thermoplastic resin core sheet and an IC chip bearing a conductive projection formed on an electrode of the IC chip, the IC chip being embedded in the core sheet in such a manner that the exposed top surface of the conductive projection is made flush with the main surface of the core sheet. A conductive layer pattern formed on the main surface of the core sheet is extended for contact with the exposed top surface.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: March 5, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida
  • Patent number: 4931853
    Abstract: An IC card comprises a thermoplastic resin core sheet and an IC chip bearing a conductive projection formed on an electrode of the IC chip, the IC chip being embedded in the core sheet in such a manner that the exposed top surface of the conductive projection is made flush with the main surface of the core sheet. A conductive layer pattern formed on the main surface of the core sheet is extended for contact with the exposed top surface.
    Type: Grant
    Filed: September 6, 1989
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida
  • Patent number: 4754319
    Abstract: In an IC card according to the present invention, a base sheet formed of thermoplastic material is sandwiched between a substrate sheet and a dummy sheet both formed of nonplastic material lower in thermoplasticity than the base sheet. The substrate sheet is fitted with at least one IC chip and input/output terminals electrically connected to the IC chip. First and second cover sheets formed of thermoplastic material are put individually on the outer surfaces of the substrate sheet and the dummy sheet. The cover sheet on the substrate sheet is formed with apertures through which the input/output terminals are exposed to the outside.
    Type: Grant
    Filed: September 11, 1987
    Date of Patent: June 28, 1988
    Assignees: Kabushiki Kaisha Toshiba, Shoei Printing Company Limited
    Inventors: Tamio Saito, Masayuki Ohuchi, Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Ko Kishida, Takanori Kisaka
  • Patent number: 4751126
    Abstract: A circuit board is prepared such that at least two resin substrates are laminated and bonded by thermocompression, a circuit pattern made of a resin composition containing a conductor material is formed on at least one of opposing surfaces of the substrates, a region of the substrate which corresponds to a specific portion of the circuit pattern is recessed, the specific portion of the circuit projects into the recess in accordance with plastic deformation of the substrates and the circuit pattern which is caused by thermocompression bonding, and the specific portion of the circuit pattern constitutes an exposed portion. Multilayer or three-dimensional wiring can be easily achieved in the circuit board.
    Type: Grant
    Filed: July 2, 1986
    Date of Patent: June 14, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Masayuki Ohuchi, Tamio Saito
  • Patent number: 4704318
    Abstract: There is disclosed a wiring substrate comprising a wiring circuit pattern formed on a metal substrate with an insulating resinous layer interposed therebetween. In this wiring substrate, the insulating resinous layer is formed of a high molecular composition comprising thermosetting 1,2-polybutadiene containing 5 to 30% by weight of a high molecular softening agent such as hydrogenated polybutadiene. A method of manufacturing such a wiring substrate is also disclosed, wherein a light-reflecting pigment is included in the insulating resinous layer for the convenience of the subsequent laser trimming.
    Type: Grant
    Filed: March 12, 1986
    Date of Patent: November 3, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Saito, Hirosi Oodaira
  • Patent number: 4694138
    Abstract: A conductor path is formed by providing an insulating substrate having a surface region which is formed of an insulating composition. The insulating composition contains an organic polymeric material and at least one metal source. The metal source is a metallic powder and/or an organic compound chemically combining a metal or metals. The surface region of the substrate is selectively heated along a predetermined pattern, thereby decomposing and evaporating the organic polymeric material at the heated portion and welding the metal in the heated portion so as to form a conductor path formed of the metal.
    Type: Grant
    Filed: November 30, 1984
    Date of Patent: September 15, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirosi Oodaira, Haruko Suzuki, Masayuki Saito, Masayuki Ohuchi
  • Patent number: 4635356
    Abstract: Terminal-equipped electronic elements, such as chip resistors and chip diodes, are arranged such that one surface of each terminal contacts one surface of a support board, the support board being placed to face a flat plate through a spacer. An electrically insulative liquid synthetic resin is injected between the support board and the flat board and cured to form a synthetic resin layer burying the electronic elements. The support board, flat board and spacer are peeled from the electronic elements and the synthetic resin layer to expose one surface of the terminal of each electronic element on one surface of the synthetic resin layer. A conductive pattern is formed on the synthetic resin layer by screen printing to connect the terminals of the electronic elements.
    Type: Grant
    Filed: August 15, 1985
    Date of Patent: January 13, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ohuchi, Hirosi Oodaira, Kenichi Yoshida
  • Patent number: 4584456
    Abstract: A resistor is formed by locally heating an insulating material layer between conductors to convert the heated material into a first resistor element. A second resistor element is formed to contact the first resistor element while measuring the resistance between the conductors, until a desired resistor composed of the first and second resistor elements and having a predetermined resistance value is obtained.
    Type: Grant
    Filed: September 7, 1983
    Date of Patent: April 22, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hirosi Oodaira, Haruko Suzuki, Masayuki Saito, Nobuo Iwase
  • Patent number: 4572843
    Abstract: A method for producing a capacitor includes the steps of: forming on a dielectric layer formed on a first electrode, an insulating composition, e.g., an organic polymeric compound containing a metal powder or an organometallic compound as a metal source, which is rendered conductive upon heating by radiation; and locally and gradually heating the insulating composition layer so as to form a second conductive electrode while measuring an increase in a capacitance between a conductor end portion for measuring a capacitance and the first electrode. According to this method, a capacitor having a precise capacitance can be formed.
    Type: Grant
    Filed: February 1, 1985
    Date of Patent: February 25, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Saito, Haruko Suzuki, Hirosi Oodaira
  • Patent number: 4412377
    Abstract: A method for manufacturing a hybrid integrated circuit device comprising a step of forming an Al.sub.2 O.sub.3 layer on a metal substrate, a step of forming on the Al.sub.2 O.sub.3 layer a resist layer having a pattern opposite to that of a copper layer which will be formed on the Al.sub.2 O.sub.3 layer by a later step, a step of forming the copper layer on the Al.sub.2 O.sub.3 layer using the resist layer as a mask, a step of impregnating thermosetting material into both the Al.sub.2 O.sub.3 layer and the copper layer, and a step of providing at least one semiconductor element on the copper layer.
    Type: Grant
    Filed: January 21, 1982
    Date of Patent: November 1, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Nagashima, Hiroshi Matsumoto, Masataka Tanaka, Hirosi Oodaira, Nobuo Iwase