Patents by Inventor Hirosuke Koumyoji

Hirosuke Koumyoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7330043
    Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: February 12, 2008
    Assignee: Fujitsu Limited
    Inventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
  • Publication number: 20050156589
    Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 21, 2005
    Inventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
  • Patent number: 6885212
    Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: April 26, 2005
    Assignee: Fujitsu Limited
    Inventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
  • Publication number: 20030234661
    Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
    Type: Application
    Filed: February 3, 2003
    Publication date: December 25, 2003
    Applicant: Fujitsu Limited
    Inventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase