Abstract: A combined electric power generations' supply system includes an AC power generator that supplies power by off grid independent operation, a DC power supply device, an inverter that converts DC power output by the DC power supply device into AC power. The rotation calculation unit calculates a value relating to a rotation of a rotor when driving the virtual power generator according to an active power command based on a rotor model calculates a value relating to the rotation of the rotor of the virtual power generator and the active power command. The output determination unit determines values relating to an active power and a reactive power to be output to the inverter based on the calculated value relating to the rotation. The modulation control unit performs control of a pulse width modulation of the inverter based on the determined value relating to the active power and reactive power.

Abstract: A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L1 denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.

Abstract: A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L1 denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.

Abstract: A lead frame is produced using a thin metal plate to form a stage for mounting a semiconductor chip, a plurality of leads encompassing the stage, and a frame portion for fixing the stage and leads together. Surfaces of the internal ends of the leads are each expanded in a longitudinal direction and/or a width direction so as to form expanded portions; cutouts are formed in the internal ends of the leads; or the internal ends of the leads are extended outwardly so as to form extended portions. A sealing resin is molded to incorporate the lead frame so as to produce a semiconductor package. Hence, it is possible to increase the overall contact area between the leads and the sealing resin; it is possible to increase the adhesion between the leads and the sealing resin; thus, it is possible to improve the reliability of the semiconductor package in manufacturing.

Abstract: A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L1 denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.