Abstract: According to one embodiment, a memory system includes a storage device and a controller. The controller is configured to control data write to the storage device and data read from the storage device based on a request from a host device. The controller is configured to maintain or invert logic of first data that is part of transmit data to be transferred to the storage device by N bits per 1 unit interval (UI) through N data signal lines (N is a natural number of one or more), create second data indicating presence or absence of inversion of the logic of the first data, and transfer the first data and the second data to the storage device through the N data signal lines.

Abstract: A storage device includes a non-volatile memory including a buffer of a first size and a controller. The controller is configured to transmit a control command to the non-volatile memory, and then repeat a process including a first process of changing a phase value of a timing signal indicating timing to read or write data from or to the non-volatile memory and a second process of reading or writing data having a second size smaller than the first size from or to the non-volatile memory in synchronization with the timing signal of the changed phase value, a certain plurality of times without transmitting any other control command to the non-volatile memory during repetition of the process.

Abstract: According to one embodiment, a memory system includes a storage device and a controller. The controller is configured to control data write to the storage device and data read from the storage device based on a request from a host device. The controller is configured to maintain or invert logic of first data that is part of transmit data to be transferred to the storage device by N bits per 1 unit interval (UI) through N data signal lines (N is a natural number of one or more), create second data indicating presence or absence of inversion of the logic of the first data, and transfer the first data and the second data to the storage device through the N data signal lines.

Abstract: A storage device includes a non-volatile memory including a buffer of a first size and a controller. The controller is configured to transmit a control command to the non-volatile memory, and then repeat a process including a first process of changing a phase value of a timing signal indicating timing to read or write data from or to the non-volatile memory and a second process of reading or writing data having a second size smaller than the first size from or to the non-volatile memory in synchronization with the timing signal of the changed phase value, a certain plurality of times without transmitting any other control command to the non-volatile memory during repetition of the process.

Abstract: In a power supply apparatus of an electric spark (discharge) machine for generating high frequency pulse by a switching circuit from a DC power supply, stepping up the voltage by a high frequency transformer, generating a dire current by a rectifier, and feeding the DC power to the electric spark gap, the voltage of OP amplifier (221) for detecting an output voltage and an OP amplifier (222) for detecting an output current and converting it to a voltage are inputted to a summation OP amplifier (223). The output voltage and the output current are controlled so as to have a negative proportional linear relation via feedback circuit (220) for performing feedback to a fly-back switching circuit (210) through a voltage comparison/subtraction OP amplifier (224) for comparing and subtracting the sum of the voltages with and from a reference voltage.