Patents by Inventor Hirotaka HORIE

Hirotaka HORIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220334802
    Abstract: An apparatus includes: a product-sum operation circuit that executes a product-sum operation with a plurality of input values quantized by power expression and plurality of weigh coefficients quantized by power expression corresponding to respective input values, in which an exponent of each of the input values is expressed by a fraction having a predetermined divisor in a denominator, an exponent of each of the weigh coefficients is expressed by a fraction having the divisor in a denominator, the product-sum operation circuit executes the product-sum operation using a plurality of addition multipliers based on a remainder when a value obtained by adding a numerator related to the exponent of each of the input values and a numerator related to the exponent of each of the weigh coefficients is divided as a dividend, and each of the addition multipliers is a floating-point number with an exponent part having a radix of 2.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 20, 2022
    Applicant: Sony Group Corporation
    Inventors: Satoshi TAKAGI, Koji KIYOTA, Hirotaka HORIE
  • Patent number: 10707140
    Abstract: A method for evaluating surface defects of a substrate to be bonded: preparing a mirror-polished silicon single crystal substrate; inspecting surface defects on the mirror-polished silicon single crystal substrate; depositing a polycrystalline silicon layer on a surface of the silicon single crystal substrate subjected to the defect inspection; performing mirror edge polishing to the silicon single crystal substrate having the polycrystalline silicon layer deposited thereon; polishing a surface of the polycrystalline silicon layer; inspecting surface defects on the polished polycrystalline silicon layer; and comparing coordinates of defects detected at the step of inspecting the surface defects on the silicon single crystal substrate with counterparts detected at the step of inspecting the surface defects on the polycrystalline silicone layer and determining quality of the silicon single crystal substrate having the polycrystalline silicon layer as a substrate to be bonded on the basis of presence/absence of
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 7, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazuya Sato, Hiromasa Hashimoto, Tsuyoshi Nishizawa, Hirotaka Horie
  • Publication number: 20190181059
    Abstract: A method for evaluating surface defects of a substrate to be bonded: preparing a mirror-polished silicon single crystal substrate; inspecting surface defects on the mirror-polished silicon single crystal substrate; depositing a polycrystalline silicon layer on a surface of the silicon single crystal substrate subjected to the defect inspection; performing mirror edge polishing to the silicon single crystal substrate having the polycrystalline silicon layer deposited thereon; polishing a surface of the polycrystalline silicon layer; inspecting surface defects on the polished polycrystalline silicon layer; and comparing coordinates of defects detected at the step of inspecting the surface defects on the silicon single crystal substrate with counterparts detected at the step of inspecting the surface defects on the polycrystalline silicone layer and determining quality of the silicon single crystal substrate having the polycrystalline silicon layer as a substrate to be bonded on the basis of presence/absence of
    Type: Application
    Filed: July 26, 2017
    Publication date: June 13, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazuya SATO, Hiromasa HASHIMOTO, Tsuyoshi NISHIZAWA, Hirotaka HORIE