Patents by Inventor Hirotaka Katou

Hirotaka Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8530801
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 10, 2013
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Publication number: 20090226293
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 10, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Patent number: 5953620
    Abstract: A method for fabricating a bonded SOI wafer is provided in which no void is produced during a waiting period from the completion of a bonding step to the start of a bonding thermal processing step without a special restriction. The method for fabricating a bonded SOI wafer includes a bonding step in which an active wafer, which has been single- or both-side mirror polished and thermal oxidation processed to form an insulating layer of a predetermined thickness, is pressed and bonded to a single- or both-side mirror polished base wafer; and a bonding thermal processing step for carrying out a bonding thermal processing for bonding the wafer, in which a hydrophobic processing step for the base wafer and a hydrophilic processing step for the active wafer are carried out before the bonding step.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: September 14, 1999
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Hirotaka Katou, Hiroshi Furukawa, Kazuaki Fujimoto