Patents by Inventor Hirotaka Kizuki

Hirotaka Kizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7307490
    Abstract: A high frequency switch device has SPDT(A), SPDT(B), and SPDT(C) switches, each having one pole and a first port and a second port, wherein the second port of the SPDT(A) is grounded via a terminating resistor and the second port of the SPDT(B) is grounded via a terminating resistor, respectively, and the first port of the SPDT(A) and the first port of the SPDT(B) are respectively connected to the first port and the second port of the SPDT(C).
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: December 11, 2007
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Sharp Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Noriyuki Tanino, Junichi Somei
  • Publication number: 20050077978
    Abstract: A high frequency switch device has SPDT(A), SPDT(B), and SPDT(C) switches, each having one pole and a first port and a second port, wherein the second port of the SPDT(A) is grounded via a terminating resistor and the second port of the SPDT(B) is grounded via a terminating resistor, respectively, and the first port of the SPDT(A) and the first port of the SPDT(B) are respectively connected to the first port and the second port of the SPDT(C).
    Type: Application
    Filed: October 5, 2004
    Publication date: April 14, 2005
    Applicants: Mitsubishi Denki Kabushiki Kaisha, Sharp Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Noriyuki Tanino, Junichi Somei
  • Patent number: 6506618
    Abstract: An undoped GaAs layer is formed on a GaAs substrate. Thallium is adhered to the undoped GaAs layer to a thickness of at least one atomic layer. After adhesion of thallium, GaInNAs is epitaxially grown on the undoped GaAs layer by chemical vapor deposition.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: January 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Yasutomo Kajikawa
  • Patent number: 6358316
    Abstract: In a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer with the insulating mask pattern is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer grown in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown crystal layer.
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: March 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Norio Hayafuji, Tatsuya Kimura
  • Patent number: 6096617
    Abstract: A compound semiconductor device is manufactured by forming a carbon-doped compound semiconductor device at a predetermined growth temperature on a compound semiconductor substrate, stopping the growth and changing the growth temperature of the compound semiconductor layer, including the carbon-doped compound semiconductor layer, to a predetermined temperature under an atmosphere comprising an alkylarsine, thereby avoiding the formation of free atomic hydrogen and preventing hydrogen contamination of the C-doped compound semiconductor layer. As a result, the amount of coupling between hydrogen and carbon in the carbon-doped compound semiconductor layer is significantly reduced, thereby preventing lowering of the carbon carrier concentration. The present method enables formation of a C-doped GaAs base layer without deterioration of electrical characteristics, and formation of a laser having a second clad layer of C-doped compound semiconductor layer with improved reliability.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: August 1, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotaka Kizuki
  • Patent number: 5991322
    Abstract: A semiconductor optical device includes a first semiconductor layer, and a diffraction grating disposed on the first semiconductor layer. The diffraction grating includes portions of a superlattice layer grown on the first semiconductor layer and including alternatingly arranged second semiconductor layers of a semiconductor material in which mass transport hardly occurs during growth of other semiconductor layers and third semiconductor layers of a semiconductor material different from the material of the second semiconductor layers. The device includes a fourth semiconductor layer burying the diffraction grating. In this structure, since the second semiconductor layers are included in the diffraction grating, the shape of the diffraction grating is maintained during the vapor phase deposition of the fourth semiconductor layer. Therefore, the thickness, amplitude, and pitch of the diffraction grating that determine the optical coupling constant are controlled with high precision.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: November 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Takiguchi, Katsuhiko Goto, Hirotaka Kizuki
  • Patent number: 5948161
    Abstract: In fabricating a semiconductor device, a semiconductor layer containing Al and a cap layer not containing Al are successively grown on a semiconductor substrate and are placed in a halogen gas environment where a chemical reaction between a halogen and an oxide film naturally formed on the cap layer removes the oxide film. Then, without exposing the layer to the atmosphere, the halogen gas environment is replaced with a dry-etching environment and the cap layer is dry-etched to a desired depth. Then, without exposing a semiconductor layer to the atmosphere, the dry-etching environment is replaced with a crystal growth environment. Subsequently, another semiconductor layer is grown on the semiconductor layer. A regrowth interface of excellent cleanliness is realized and the crystallinity of the regrown semiconductor layer is improved.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: September 7, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotaka Kizuki
  • Patent number: 5882952
    Abstract: A method of fabricating a semiconductor device includes: forming multiatomic steps by MOCVD on a (110) semiconductor substrate inclined at an angle toward the ?001! direction or the ?111! direction; and growing at least one double heterostructure including a first compound semiconductor and a second compound semiconductor having a smaller band gap than the first compound semiconductor to form quantum wires of the second compound semiconductor at edges of the multiatomic steps. Multiatomic steps having step edges along the longitudinal direction of the wire have improved linearity, and thus, quantum wires can be fabricated with improved controllability.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: March 16, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Motoharu Miyashita
  • Patent number: 5835516
    Abstract: A method of fabricating a semiconductor laser device includes successively forming an active layer and upper cladding layers on a lower cladding layer, etching and removing portions except regions of the upper cladding layers where a current is to flow to form a stripe-shaped ridge structure, and forming a buffer layer comprising Al.sub.x Ga.sub.1-x As having an Al composition ratio x of 0 to 0.3 on a surface of the upper cladding layers exposed by the etching and forming a current blocking layer of first conductivity type Al.sub.y Ga.sub.1-y As having an Al composition ratio y of at least 0.5 on the buffer layer to bury portions of the upper cladding layers which are not removed by the etching process. Therefore, since the layer grown on the upper cladding layer exposed by etching of AlGaAs or GaAs having a low Al composition ratio (0-0.3), three-dimensional growth of and crystalline defects in the buffer layer are suppressed.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Motoharu Miyashita, Hirotaka Kizuki, Yasuaki Yoshida, Yutaka Mihashi, Yasutomo Kajikawa, Shoichi Karakida, Yuji Ohkura
  • Patent number: 5805628
    Abstract: A semiconductor laser device includes a semiconductor substrate of a first conductivity type; opposed light emitting facets; a double heterojunction structure disposed on the semiconductor substrate and including an optical waveguide that extends between the facets and comprises a light emitting region and a lens region, the lens region being between the light emitting region and one of the facets, the double heterojunction structure including a plurality of AlGaAs series compound semiconductor layers which are thicker in the light emitting region than in the lens region; and a current blocking structure disposed on both sides of the double heterojunction structure and including a lower AlGaAs series compound semiconductor layer of the first conductivity type, an intermediate AlGaAs series compound semiconductor layer of a second conductivity type, opposite the first conductivity type, and an upper AlGaAs series compound semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: September 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Karakida, Norio Hayafuji, Tatsuya Kimura, Motoharu Miyashita, Hirotaka Kizuki, Takashi Nishimura
  • Patent number: 5796127
    Abstract: A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: August 18, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto, Hirotaka Kizuki
  • Patent number: 5782979
    Abstract: A substrate holder employed for MOCVD and supporting a wafer on which crystal growth proceeds includes a molybdenum holder body, a GaAs polycrystalline film with a flat surface grown on a part of the surface of the molybdenum holder body where the wafer is absent, and an InP polycrystalline film grown on the GaAs polycrystalline film. Each of the polycrystalline films is grown to a thickness of 0.3 .mu.m or more at a temperature higher than the epitaxial growth temperature of 575.degree. C. During the MOCVD process, the emissivity of the molybdenum substrate holder is stable at a value near the emissivity of the wafer on the substrate holder and, therefore, the decomposition ratio of PH.sub.3 gas on the substrate holder is stable at a value near the decomposition ratio on the wafer, whereby any variation of the incorporation ratio of P atoms in the grown InGaAsP, i.e., a variation of the composition of the InGaAsP, is reduced and run-to-run variations of the composition of the grown crystal are reduced.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: July 21, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Kaneno, Hirotaka Kizuki, Masayoshi Takemi, Kenzo Mori
  • Patent number: 5714006
    Abstract: A method of growing a compound semiconductor layer includes epitaxially growing a III-V compound semiconductor layer including nitrogen (N) for as the Group V element on a front surface of a semiconductor substrate of cadmium telluride (CdTe). Therefore, the atoms of the crystal lattice of the III-V compound semiconductor layer are periodically lattice-matched with the atoms of the crystal lattice of the CdTe semiconductor substrate, whereby the III-V compound semiconductor layer is epitaxially grown with high crystalline quality.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: February 3, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Yasutomo Kajikawa
  • Patent number: 5679962
    Abstract: A semiconductor device includes a semi-insulating semiconductor substrate, a semiconductor layer structure including at least an undoped layer of a first semiconductor, an undoped spacer layer of a second semiconductor having an electron affinity smaller than that of the first semiconductor, and an n type electron supply layer of the second semiconductor successively laminated on the substrate, the undoped layer having a flat top surface and a flat rear surface on the flat top surface of the undoped spacer layer, having, at a top surface, a concavo-convex periodic structure, and a flat rear surface, the n-type electron supply layer of the second semiconductor having a flat top surface and a rear surface that buries concavities of the concavo-convex structure of the undoped spacer layer, and a plurality of periodically arranged Schottky electrodes on the flat top surface of the n type electron supply layer, arranged in a direction perpendicular to the concavo-convex periodic structure of the undoped spacer lay
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: October 21, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotaka Kizuki
  • Patent number: 5608749
    Abstract: A semiconductor laser diode having a selective PHS structure includes a semiconductor substrate having opposite first and second main surfaces, a laser diode structure disposed on the first main surface, and a PHS electrode selectively buried in the second main surface wherein the laser diode structure is located in an area defined by a first pair of parallel lines running in a direction perpendicular to a resonator length direction and a second pair of parallel lines located at the side surfaces of the semiconductor substrate, the first pair of lines being located internally of front and rear facets of the semiconductor substrate, and the PHS electrode has a length in the resonator length direction no shorter than the active region in the resonator length direction. The heat radiating characteristic is improved, especially at the laser beam emitting facet.
    Type: Grant
    Filed: July 21, 1993
    Date of Patent: March 4, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotaka Kizuki
  • Patent number: 5602414
    Abstract: In a method for fabricating an infrared detector, initially, a CdHgTe layer of a first conductivity type is produced on a front surface of a semiconductor substrate, a plurality of spaced apart CdHgTe regions of a second conductivity type, opposite the first conductivity type, are produced at the surface of the first conductivity type CdHgTe layer, and part of the surface of the first conductivity type CdHgTe layer between the second conductivity type CdHgTe regions is selectively irradiated with a charged particle beam to evaporate Hg atoms from that part, whereby a CdHgTe separation region of the first conductivity type and having a Cd composition larger than that of the first conductivity type CdHgTe layer is produced penetrating through the first conductivity type CdHgTe layer and surrounding each of the second conductivity type CdHgTe regions. Therefore, a highly-integrated high-resolution infrared detector with no crosstalk between pixels is achieved.
    Type: Grant
    Filed: June 16, 1994
    Date of Patent: February 11, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kotaro Mitsui, Zenpei Kawazu, Kazuo Mizuguchi, Seiji Ochi, Yuji Ohkura, Norio Hayafuji, Hirotaka Kizuki, Mari Tsugami, Akihiro Takami, Manabu Katoh
  • Patent number: 5541950
    Abstract: A semiconductor laser including a semiconductor substrate of a first conductivity type; a semiconductor multilayer structure disposed on the substrate and including a first cladding layer of the first conductivity type, an active layer, a second cladding layer of a second conductivity type, opposite the first conductivity type, and a current blocking layer of the first conductivity type; a laser light emitting facet; a stripe-shaped V groove extending in a resonator length direction transverse to the laser light emitting facet and penetrating in a depth direction into a part of the semiconductor multilayer structure, including into the second cladding layer, the stripe-shaped V groove having a width transverse to the resonator length direction and the depth direction wherein at least one of the depth and width of the stripe-shaped V groove has a first dimension adjacent the laser light emitting facet and a second dimension, different from the first dimension, within the semiconductor laser spaced from the las
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Shoichi Karakida
  • Patent number: 5539763
    Abstract: An integrated semiconductor laser and light modulator includes a semiconductor laser disposed at a first region on a semiconductor substrate, a light modulator of an electric field absorbing type disposed at a second region on the semiconductor substrate adjacent to the first region for outputting a modulated light by transmitting or absorbing the laser light generated in the semiconductor laser, a semiconductor laminated layer structure including a quantum well structure layer disposed in the first region and the second region on the semiconductor substrate, and a lattice mismatched layer having a lattice constant smaller than that of the semiconductor substrate, disposed on a part of the semiconductor laminated layer structure, in the second region. It is possible to enhance the transmission efficiency of the laser light to the light modulator and the quality of the active layer of the semiconductor laser and the light absorption layer of the light modulator.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: July 23, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayoshi Takemi, Hirotaka Kizuki
  • Patent number: 5459747
    Abstract: A semiconductor optical device includes a first semiconductor layer, and a diffraction grating disposed on the first semiconductor layer. The diffraction grating includes portions of a superlattice layer grown on the first semiconductor layer and including alternatingly arranged second semiconductor layers of a semiconductor material in which mass transport hardly occurs, during growth of other semiconductor layers and third semiconductor layers of a semiconductor material different from the material of the second semiconductor layers. The device includes a fourth semiconductor layer burying the diffraction grating. In this structure, since the second semiconductor layers are included in the diffraction grating, the shape of the diffraction grating is maintained during the vapor phase deposition of the fourth semiconductor layer. Therefore, the thickness, amplitude, and pitch of the diffraction grating that determine the optical coupling constant are controlled with high precision.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: October 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Takiguchi, Katsuhiko Goto, Hirotaka Kizuki
  • Patent number: 5426658
    Abstract: A semiconductor laser device including a semiconductor substrate; a plurality of semiconductor layers including an AlGaAs layer epitaxially grown on said semiconductor substrate; a ridge having a reverse mesa shape and opposed sides formed of said plurality of semiconductor layers; an Al.sub.x Ga.sub.1-x As low temperature buffer layer (0.ltoreq..times..ltoreq.1) disposed on said AlGaAs layer at opposite sides of said ridge; a first semiconductor layer epitaxially disposed on said low temperature buffer layer at opposite sides of said ridge; and a second semiconductor layer epitaxially disposed on said ridge and said first semiconductor layer.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: June 20, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Kaneno, Hirotaka Kizuki, Norio Hayafuji, Tetsuo Shiba, Hitoshi Tada