Patents by Inventor Hirotaka Komatsubara
Hirotaka Komatsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7935934Abstract: The photosensor comprises an insulating layer formed over the silicon substrate; an ultraviolet photosensitive element formed over the insulating layer and having a first diffusion layer, a second diffusion layer provided spaced away from the first diffusion layer, and a third diffusion layer connected with the first diffusion layer and the second diffusion layer respectively; and a visible light photosensitive element formed over the insulating layer with being spaced away from the ultraviolet photosensitive element, and having a fourth diffusion layer, a fifth diffusion layer provided spaced away from the fourth diffusion layer, and a sixth diffusion layer connected with the fourth diffusion layer and the fifth diffusion layer respectively.Type: GrantFiled: December 26, 2008Date of Patent: May 3, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Hirotaka Komatsubara
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Patent number: 7709350Abstract: A method for manufacturing a semiconductor elemental device including an SOI structure in which an SOI layer is laminated, includes the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and forming an oxidation-resistant film over the pad oxide film; forming a resist mask in a region corresponding to each of the transistor forming regions, and etching the oxidation-resistant film and the pad oxide film with the resist mask as a mask to expose the SOI layer of the device isolation region; removing the resist mask and oxidizing the exposed SOI layer by a LOCOS method using the oxidation-resistant film to form a field oxide film; and implanting amorphization ions in an edge portion formed in the SOI layer upon formation of the field oxide film to amorphize the edge portion.Type: GrantFiled: January 23, 2006Date of Patent: May 4, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Hirotaka Komatsubara
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Publication number: 20090179156Abstract: The photosensor comprises an insulating layer formed over the silicon substrate; an ultraviolet photosensitive element formed over the insulating layer and having a first diffusion layer, a second diffusion layer provided spaced away from the first diffusion layer, and a third diffusion layer connected with the first diffusion layer and the second diffusion layer respectively; and a visible light photosensitive element formed over the insulating layer with being spaced away from the ultraviolet photosensitive element, and having a fourth diffusion layer, a fifth diffusion layer provided spaced away from the fourth diffusion layer, and a sixth diffusion layer connected with the fourth diffusion layer and the fifth diffusion layer respectively.Type: ApplicationFiled: December 26, 2008Publication date: July 16, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Hirotaka KOMATSUBARA
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Publication number: 20080102572Abstract: The present invention provides a method of manufacturing a semiconductor device, which is simple in manufacturing process and easy to control formed positions of a tensile film and a compressive film and their thicknesses. An n-type MOSFET and a p-type MOSFET are formed on a semiconductor substrate, and the tensile film is formed on the n-type MOSFET. Thereafter, a protective film is formed on the entire surface of the semiconductor substrate. After a compressive film is formed on the protective film, the compressive film provided on the n-type MOSFET is removed by etching using the protective film as an etching stopper.Type: ApplicationFiled: October 5, 2007Publication date: May 1, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Hirotaka Komatsubara
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Patent number: 7170182Abstract: A semiconductor device has interconnecting lines disposed side by side in a dielectric film. Mutually adjacent pairs of interconnecting lines are separated by a substantially constant distance from top to bottom, but the width of each interconnecting line varies from top to bottom. For example, the interconnecting lines may have T-shaped or trapezoidal cross sections, interconnecting lines having wide tops alternating with interconnecting lines having wide bottoms. These cross-sectional shapes can be formed by simple fabrication processes. Since the facing sides of mutually adjacent interconnecting lines do not form mutually parallel vertical planes and therefore do not function as parallel plate electrodes, the interconnect capacitance is reduced.Type: GrantFiled: March 31, 2004Date of Patent: January 30, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Hirotaka Komatsubara
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Publication number: 20060186471Abstract: A semiconductor device with simple device structure enables reduction in the number of manufacturing steps and the manufacturing cost. A gate insulation film and a gate electrode are formed in a certain area on a semiconductor substrate. A semiconductor substrate non-removed section is formed under the gate insulation film, and semiconductor substrate removed regions are formed around the non-removed section by etching. After an LDD source region and an LDD drain region which have low impurity concentration are formed in the removed regions, sidewalls are formed on the side faces of the gate electrode, the gate insulation film, and the non-removed section. After that, a source region and a drain region with high impurity concentration are formed in the removed regions around the sidewalls.Type: ApplicationFiled: April 27, 2006Publication date: August 24, 2006Applicant: Oki Electric Industry Co., Ltd.Inventor: Hirotaka Komatsubara
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Publication number: 20060166412Abstract: The present invention provides a method for manufacturing a semiconductor elemental device comprising an SOI structure in which an SOI layer is laminated, comprising the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and forming an oxidation-resistant film over the pad oxide film; forming a resist mask in a region corresponding to each of the transistor forming regions, and etching the oxidation-resistant film and the pad oxide film with the resist mask as a mask to expose the SOI layer of the device isolation region; removing the resist mask and oxidizing the exposed SOI layer by a LOCOS method using the oxidation-resistant film to form a field oxide film; and implanting amorphization ions in an edge portion formed in the SOI layer upon formation of the field oxide film to amorphize the edge portion.Type: ApplicationFiled: January 23, 2006Publication date: July 27, 2006Inventor: Hirotaka Komatsubara
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Patent number: 6977205Abstract: This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130 in an element region S; forming a metal oxide film 180 for generating a fixed electric charge on the nitride film 150 and on the silicon layer 130 in an element isolation region A; forming a field oxide film 160 in the element isolation region A by implementing an oxidation treatment; and removing the metal oxide film 180 on the nitride film 150, the nitride film 150 and the pad oxide film 140. In the semiconductor device, the threshold voltage of a parasitic transistor is made high and prevented from turning on, and the influence of leak current is reduced and the hump characteristic of element is restrained.Type: GrantFiled: January 28, 2004Date of Patent: December 20, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Hirotaka Komatsubara
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Publication number: 20050212043Abstract: A semiconductor device with simple device structure enables reduction in the number of manufacturing steps and the manufacturing cost. A gate insulation film and a gate electrode are formed in a certain area on a semiconductor substrate. A semiconductor substrate non-removed section is formed under the gate insulation film, and semiconductor substrate removed regions are formed around the non-removed section by etching. After an LDD source region and an LDD drain region which have low impurity concentration are formed in the removed regions, sidewalls are formed on the side faces of the gate electrode, the gate insulation film, and the non-removed section. After that, a source region and a drain region with high impurity concentration are formed in the removed regions around the sidewalls.Type: ApplicationFiled: October 13, 2004Publication date: September 29, 2005Inventor: Hirotaka Komatsubara
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Publication number: 20050062129Abstract: This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130 in an element region S; forming a metal oxide film 180 for generating a fixed electric charge on the nitride film 150 and on the silicon layer 130 in an element isolation region A; forming a field oxide film 160 in the element isolation region A by implementing an oxidation treatment; and removing the metal oxide film 180 on the nitride film 150, the nitride film 150 and the pad oxide film 140. In the semiconductor device, the threshold voltage of a parasitic transistor is made high and prevented from turning on, and the influence of leak current is reduced and the hump characteristic of element is restrained.Type: ApplicationFiled: January 28, 2004Publication date: March 24, 2005Inventor: Hirotaka Komatsubara
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Publication number: 20040232555Abstract: A semiconductor device has interconnecting lines disposed side by side in a dielectric film. Mutually adjacent pairs of interconnecting lines are separated by a substantially constant distance from top to bottom, but the width of each interconnecting line varies from top to bottom. For example, the interconnecting lines may have T-shaped or trapezoidal cross sections, interconnecting lines having wide tops alternating with interconnecting lines having wide bottoms. These cross-sectional shapes can be formed by simple fabrication processes. Since the facing sides of mutually adjacent interconnecting lines do not form mutually parallel vertical planes and therefore do not function as parallel plate electrodes, the interconnect capacitance is reduced.Type: ApplicationFiled: March 31, 2004Publication date: November 25, 2004Inventor: Hirotaka Komatsubara
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Patent number: 6673660Abstract: According to the present invention, a semiconductor device to use a SOI substrate performing insulation by a LOCOS method in which an oxide resistivety film provided on a silicon layer is used, includes steps of: implanting impurity in a LOCOS edge which is a silicon layer under bird's beak of the field oxide film with the oxide resistant film as a mask after a field oxide film is formed and forming a high density impurity area having impurity density higher than impurity density of an impurity diffusion layer formed on the silicon layer, and removing a pad oxide film after a heat treatment is performed for the field oxide film after the high density impurity area is formed. Therefore, a method of manufacturing the semiconductor device at a lower cost to suppress occurrence of hump and to prevent a MOSFET characteristic from deteriorating can be provided.Type: GrantFiled: January 31, 2002Date of Patent: January 6, 2004Assignee: Oki Electric Industry Co, Ltd.Inventor: Hirotaka Komatsubara
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Patent number: 6553339Abstract: A MOSFET simulation method for calculating a characteristic value of a MOSFET to be simulated by first numerically calculating the electric potential, electron density, hole density, and mobility inside the MOSFET from simulation conditions including various parameters of the MOSFET, and then using the electric potential, electron density, hole density, and carrier mobility is provided.Type: GrantFiled: September 14, 1999Date of Patent: April 22, 2003Assignee: Oki Electric Industry Co, Ltd.Inventor: Hirotaka Komatsubara
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Publication number: 20030068870Abstract: According to the present invention, a semiconductor device to use a SOI substrate performing insulation by a LOCOS method in which an oxide resistivety film provided on a silicon layer is used, includes steps of: implanting impurity in a LOCOS edge which is a silicon layer under bird's beak of the field oxide film with the oxide resistant film as a mask after a field oxide film is formed and forming a high density impurity area having impurity density higher than impurity density of an impurity diffusion layer formed on the silicon layer, and removing a pad oxide film after a heat treatment is performed for the field oxide film after the high density impurity area is formed. Therefore, a method of manufacturing the semiconductor device at a lower cost to suppress occurrence of hump and to prevent a MOSFET characteristic from deteriorating can be provided.Type: ApplicationFiled: January 31, 2002Publication date: April 10, 2003Inventor: Hirotaka Komatsubara