Patents by Inventor Hirotaka Maekawa

Hirotaka Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method thereof
    Patent number: 8586438
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
  • Semiconductor device and manufacturing method thereof
    Patent number: 8338831
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20120171829
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Application
    Filed: March 6, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100301350
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 2, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa