Abstract: A slave node (300) is slave equipment that operates in accordance with a control frame transmitted from a master node (200). The slave node calculates a control frame statistic that is a statistic of one or more control frames transmitted from the master equipment and estimates a master environment value based on the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock based on the estimated master environment value and estimates a frequency deviation of a slave clock based on the measured slave environment value. The slave node modifies a clock value of the slave clock based on a difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.

Abstract: A process control unit (41) causes a plurality of control-target processes to operate in a memory area of a size equal to or smaller than a limiting value x. When a stopping process is detected, a resource allocation unit (43) allocates a size of a usable memory area for each of the control-target processes as a relaxed limiting value. When the stopping process is detected, the process control unit (41) causes each of the control-target processes to perform fallback operation in a memory area of a size equal to or smaller than the relaxed limiting value allocated to the process by the resource allocation unit (43).

Abstract: A target apparatus (20) includes a bottleneck term calculation unit (22) and a running function recording scheduler (24). The bottleneck term calculation unit (22) acquires a performance graph, which is generated about run of a single program being a running subject or about run of a plurality of programs being a running subject and which indicates correspondence between a lapse of time and a load quantity being set as a load. The bottleneck term calculation unit (22) calculates, using a performance graph, a bottleneck term indicating a term where the load quantity in a limit status continues. The running function recording scheduler (24) records, during next run of the single program or of the plurality of programs to be run after the run, being an origin of generation of the performance graph, of the single program or the plurality of programs, a function which is run during the bottleneck term, using a running function recording module (23).

Abstract: A slave node (300) is slave equipment that operates in accordance with a control frame transmitted from a master node (200). The slave node calculates a control frame statistic that is a statistic of one or more control frames transmitted from the master equipment and estimates a master environment value based on the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock based on the estimated master environment value and estimates a frequency deviation of a slave clock based on the measured slave environment value. The slave node modifies a clock value of the slave clock based on a difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.

Abstract: A test device (100) runs an application program (111) that performs a series of function call processes utilizing a software platform (106), thereby testing the software platform (106). A log acquisition unit (201) runs the application program (111) a plurality of times repeatedly so as to acquire a trace log (113) including a plurality of trace results obtained by tracing the series of function call processes. A log analysis unit (202) analyzes the trace log (113) so as to estimate, as a variable attribute, each of an attribute of an argument and an attribute of a return value, of a function called by the series of function call processes. A program generation unit (203) generates a simulation program (303) which simulates the series of function call processes, using the variable attribute.

Abstract: A process control unit (41) causes a plurality of control-target processes to operate in a memory area of a size equal to or smaller than a limiting value x. When a stopping process is detected, a resource allocation unit (43) allocates a size of a usable memory area for each of the control-target processes as a relaxed limiting value. When the stopping process is detected, the process control unit (41) causes each of the control-target processes to perform fallback operation in a memory area of a size equal to or smaller than the relaxed limiting value allocated to the process by the resource allocation unit (43).

Abstract: A history storage area (106) stores, for each of a plurality of pieces of data, number of times of access via a file system. A cache management unit (119), when access to the plurality of pieces of data not via the file system occurs, sets as overwrite prohibition data and caches in a disc cache area (108), data for which number of times of access that is equal to or more than a threshold is stored in the history storage area (106), the threshold being determined based on number of times of access of the plurality of pieces of data.

Abstract: A built-in apparatus includes a response time buffer (11) that stores a response time, a calculation result buffer (14) that stores a calculated frame, and a transmission part (130). The transmission part (130) obtains second data and start processing for calculating a frame check sequence from the second data, upon receiving a transmission command (310), judges whether frame transmission processing for generating and transmitting the second data and the frame check sequence calculated from the second data as a response frame (320) will be completed within the response time, and transmits the calculated frame stored in the calculation result buffer (14) as the response frame (320) when judging that the frame transmission processing will not be completed within the response time.

Abstract: A process monitoring device has a sending process to send communication data periodically and has a receiving process to receive the sent communication data. The receiving process includes a monitoring thread to write monitoring data in a memory at every reference interval. The sending process includes an acquiring thread to acquire the monitoring data from the memory and a sending thread to send the monitoring data to the receiving process as additional data together with the communication data. The monitoring thread judges a state of the sending process depending on how many times ago the monitoring data, which the additional data is, was generated.

Abstract: A table determination unit performs a table determination process, when an access request occurs, of determining presence/absence of access authority by referring to an authority table. A code determination unit performs a code determination process, when the access request occurs, of determining presence/absence of the access authority by executing a determination code to determine presence/absence of the access authority. An access control unit allows access in a case where it is determined by the table determination process that the access authority is present and it is determined by the code determination process that the access authority is present.

Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A data transfer apparatus (10) performs data transfer between a main storage device (12) and a peripheral device (13) such as a secondary storage device (131). The data transfer apparatus (10) estimates the frequency of occurrence of the data transfer on the basis of information such as processing executed in a processor (11), sets a transfer length shorter as the frequency of occurrence of the data transfer is higher, and instructs data transfer between the main storage device (12) and the peripheral device (13) in accordance with the transfer length being set, the transfer length indicating the amount of data transferred in one execution of the data transfer.

Abstract: A built-in apparatus includes a response time buffer (11) that stores a response time, a calculation result buffer (14) that stores a calculated frame, and a transmission part (130). The transmission part (130) obtains second data and start processing for calculating a frame check sequence from the second data, upon receiving a transmission command (310), judges whether frame transmission processing for generating and transmitting the second data and the frame check sequence calculated from the second data as a response frame (320) will be completed within the response time, and transmits the calculated frame stored in the calculation result buffer (14) as the response frame (320) when judging that the frame transmission processing will not be completed within the response time.

Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

Abstract: An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices.

Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.

Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.

Abstract: An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices.