Patents by Inventor Hirotaka Namioka

Hirotaka Namioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5179574
    Abstract: A spread PN code signal receiver having a delay locked loop (DLL) circuit in an IF or RF stage characterized in that correlation outputs to be used for the DLL circuit control are (1) a correlation output between (a) a PN code advanced in phase with respect to the received signal and (b) the received signal and (2) a correlation output between (a) a PN code delayed in phase with respect to the received signal and (b) the received signal. The correlation outputs are used to detect the lock/unlock signal in the DLL circuit. In particular, AND logic for these two correlation outputs is employed to generate the lock/unlock signal only when the DLL circuit is perfectly synchronized in phase with the received signal. With this feature, a lock state can not de detected unitl a stable lock state is obtained.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: January 12, 1993
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Shintaro Watanabe, Yasushi Yamaguchi, Shigeyuki Nakayama, Hirotaka Namioka, Hisashi Terada
  • Patent number: 5090023
    Abstract: The correlation between a PN code pattern of the synchronization preamble data of an incoming spread spectrum signal and a reference PN code pattern generated on the reception side is detected by using an SAW convolver. The gate length of the SAW convolver is shorter than the preamble data length. However, an apparatus which can obtain the true correlation output by calculating the logical multiplication of the correlation output from the SAW convolver and the validation pulse is constituted.
    Type: Grant
    Filed: October 27, 1989
    Date of Patent: February 18, 1992
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Shintaro Watanabe, Yasushi Yamaguchi, Shigeyuki Nakayama, Hirotaka Namioka, Hisashi Terada
  • Patent number: 5077754
    Abstract: A tau-dither circuit in a spread spectrum communications system wherein a first PN code with a large phase change and a second PN code without a phase change are generated in the tau-dither circuit, and the first PN code is used as a PN code for synchronous tracking to a received signal whereas the second PN code is used as a PN code for despreading of the received signal.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: December 31, 1991
    Assignee: Kabushiki Kaisha Kenwood
    Inventor: Hirotaka Namioka
  • Patent number: 5062122
    Abstract: Spread spectrum receiver includes a delay locked loop (DLL) circuit for holding the synchronization of a despread signal with a received spread spectrum signal. The DLL circuit comprises a subtracter for generating a signal representative of a subtraction between first and second correlation signals, a positive feedback amplifier for amplifying the subtraction representative signal and a window comparator for producing a lock signal when the subtraction representative signal is positioned within a window width.
    Type: Grant
    Filed: September 28, 1988
    Date of Patent: October 29, 1991
    Assignees: Kenwood Corporation, Hughes Network Systems, Inc.
    Inventors: Hiep V. Pham, Hirotaka Namioka