Patents by Inventor Hirotaka Oomori
Hirotaka Oomori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978683Abstract: A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.Type: GrantFiled: October 10, 2019Date of Patent: May 7, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Toru Hiyoshi, Hirotaka Oomori, Ren Kimura
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Patent number: 11916029Abstract: A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.Type: GrantFiled: March 10, 2020Date of Patent: February 27, 2024Assignee: Sumitomo Electric Industries, Ltd.Inventors: Mitsuhiko Sakai, Hirotaka Oomori
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Patent number: 11804465Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.Type: GrantFiled: January 21, 2020Date of Patent: October 31, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsushi Kaneda, Hirotaka Oomori, Ren Kimura, Toru Hiyoshi
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Publication number: 20230326864Abstract: A semiconductor device includes a substrate, a circuit pattern, a P-terminal, an N-terminal, an O-terminal, a first transistor chip, a second transistor chip, a first diode chip, and a second diode chip. The circuit pattern includes a first region, a second region, and a third region. The third region includes a band-shaped first branch portion, a band-shaped second branch portion, and a connection portion. The first transistor chip is mounted on the first region. The second transistor chip is mounted on the second branch portion. The first diode chip is mounted on the first region. The second diode chip is mounted on the second branch portion. The first transistor chip and the first diode chip are disposed side by side along a first direction. The second transistor chip and the second diode chip are disposed side by side along the first direction.Type: ApplicationFiled: March 11, 2021Publication date: October 12, 2023Inventors: Tatsushi KANEDA, Hirotaka OOMORI
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Publication number: 20230037158Abstract: A semiconductor module includes a base member; a circuit board provided on the base member and including a positive electrode pad, a negative electrode pad, and semiconductor devices; a housing formed in a frame shape and attached to the base member; a first electrode plate electrically coupled to the positive electrode pad and having a first flat plate portion; a second electrode plate electrically coupled to the negative electrode pad and having a second flat plate portion; and a first insulating member. The first flat plate portion and the second flat plate portion are disposed in parallel from the inside to outside of the housing. The first flat plate portion has a first external connection terminal situated outside the housing, and the second flat plate portion has a second external connection terminal situated outside the housing. The first insulating member is sandwiched between the first and the second external connection terminals.Type: ApplicationFiled: January 16, 2020Publication date: February 2, 2023Inventors: Christina LEGEN, Gerhard WOELFL, Hirotaka OOMORI, Masaki TANIYAMA, Satoshi HATSUKAWA, Takashi TSUNO
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Patent number: 11495527Abstract: A semiconductor module includes a base member including a circuit board on which a positive electrode pad and a negative electrode pad are provided and on which a semiconductor device is mounted to be electrically coupled to the positive electrode pad and the negative electrode pad, a housing that is attached to the base member so as to surround the positive electrode pad and the negative electrode pad, the housing being formed in a frame shape, a first electrode plate that is electrically coupled to the positive electrode pad, the first electrode plate having a flat plate portion, and a second electrode plate that is electrically coupled to the negative electrode pad, the second electrode plate having a flat plate portion. The flat plate portion of the first electrode plate and the flat plate portion of the second electrode plate are arranged in a parallel-plate configuration within the housing.Type: GrantFiled: August 16, 2018Date of Patent: November 8, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hirotaka Oomori, Satoshi Hatsukawa, Takashi Tsuno
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Patent number: 11417591Abstract: A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.Type: GrantFiled: January 22, 2019Date of Patent: August 16, 2022Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kenichi Sawada, Jiro Shinkai, So Tanaka, Hirotaka Oomori
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Patent number: 11393733Abstract: A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surType: GrantFiled: January 15, 2019Date of Patent: July 19, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsushi Kaneda, Yoshisumi Kawabata, So Tanaka, Hirotaka Oomori
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Publication number: 20220181281Abstract: A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.Type: ApplicationFiled: March 10, 2020Publication date: June 9, 2022Inventors: Mitsuhiko SAKAI, Hirotaka OOMORI
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Publication number: 20220130792Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.Type: ApplicationFiled: January 21, 2020Publication date: April 28, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Tatsushi KANEDA, Hirotaka OOMORI, Ren KIMURA, Toru HIYOSHI
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Patent number: 11201130Abstract: A semiconductor device includes a base plate; a metal plate above the base plate; a bonding material between the base plate and metal plate, bonding the metal plate to the base plate; an insulating plate on the metal plate; a circuit member on the insulating plate; a semiconductor element mounted on the circuit member; and a sealing material to seal a space on the base plate. The metal plate includes a bottom surface area along a periphery, exposed from the bonding material. The base plate includes a groove-shaped first recess formed along the periphery of the metal plate and faces the bottom surface area. The base plate also includes a groove-shaped second recess that is spaced apart from the first recess and that is formed on the inner side relative to the first recess. The bonding material is disposed in at least a part of the second recess.Type: GrantFiled: December 3, 2018Date of Patent: December 14, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hirotaka Oomori, Takashi Tsuno
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Patent number: 11183485Abstract: A semiconductor module 1 according to one embodiment includes a first circuit board, circuit units and a first plate member; the circuit units include a second plate member, a vertical type transistor and a second circuit board; n first circuit unit of N circuit units electrically connect a back surface side conductive region to the first input interconnection pattern of the first circuit board; (N?n) second circuit unit of the N circuit units electrically connect the third conductive pattern and the fourth conductive pattern of the second circuit board to the first control interconnection pattern and the second input interconnection pattern of the first circuit board; the first plate member electrically connects the fourth conductive pattern of the first circuit units to the second plate member of the second circuit units; and the gate electrode pad of the vertical type transistor contained in the first circuit unit is electrically connected to the first control interconnection pattern of the first circuit bType: GrantFiled: August 9, 2017Date of Patent: November 23, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hirotaka Oomori
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Publication number: 20210351092Abstract: A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.Type: ApplicationFiled: October 10, 2019Publication date: November 11, 2021Inventors: Toru HIYOSHI, Hirotaka OOMORI, Ren KIMURA
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Publication number: 20210320055Abstract: A semiconductor module includes a base member including a circuit board on which a positive electrode pad and a negative electrode pad are provided and on which a semiconductor device is mounted to be electrically coupled to the positive electrode pad and the negative electrode pad, a housing that is attached to the base member so as to surround the positive electrode pad and the negative electrode pad, the housing being formed in a frame shape, a first electrode plate that is electrically coupled to the positive electrode pad, the first electrode plate having a flat plate portion, and a second electrode plate that is electrically coupled to the negative electrode pad, the second electrode plate having a flat plate portion. The flat plate portion of the first electrode plate and the flat plate portion of the second electrode plate are arranged in a parallel-plate configuration within the housing.Type: ApplicationFiled: August 16, 2018Publication date: October 14, 2021Inventors: Hirotaka OOMORI, Satoshi HATSUKAWA, Takashi TSUNO
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Patent number: 11056456Abstract: A semiconductor apparatus includes a base plate, a metal plate disposed on the base plate, a bonding material disposed between the base plate and the metal plate to be in surface-to-surface contact with the base plate and the metal plate to bond the metal plate to the base plate, an insulating plate disposed on the metal plate, a circuit member disposed on the insulating plate to be in surface-to-surface contact with the insulating plate, a semiconductor device mounted on the circuit member, and an encapsulating material covering the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor device to encapsulate an area over the base plate, wherein a bottom face area of the metal plate along the outer perimeter of the metal plate is not covered with the bonding material, wherein the base plate has a groove-shape recess that is disposed along the outer perimeter of the metal plate to face the bottom surface area, wherein the recess has an area having a first depth and aType: GrantFiled: December 3, 2018Date of Patent: July 6, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hirotaka Oomori, Takashi Tsuno
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Publication number: 20210066236Abstract: A semiconductor apparatus includes a base plate, a metal plate disposed on the base plate, a bonding material disposed between the base plate and the metal plate to be in surface-to-surface contact with the base plate and the metal plate to bond the metal plate to the base plate, an insulating plate disposed on the metal plate, a circuit member disposed on the insulating plate to be in surface-to-surface contact with the insulating plate, a semiconductor device mounted on the circuit member, and an encapsulating material covering the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor device to encapsulate an area over the base plate, wherein a bottom face area of the metal plate along the outer perimeter of the metal plate is not covered with the bonding material, wherein the base plate has a groove-shape recess that is disposed along the outer perimeter of the metal plate to face the bottom surface area, wherein the recess has an area having a first depth and aType: ApplicationFiled: December 3, 2018Publication date: March 4, 2021Inventors: Hirotaka OOMORI, Takashi TSUNO
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Publication number: 20210066235Abstract: A semiconductor device includes a base plate; a metal plate disposed above the base plate; a bonding material disposed between the base plate and the metal plate and in surface contact with the base plate and the metal plate so as to bond the metal plate to the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate and in surface contact with the insulating plate; a semiconductor element mounted on the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space on the base plate. The metal plate includes a bottom surface area that is located along an outer periphery of the metal plate and that is not covered by the bonding material. The base plate includes a groove-shaped first recess that is formed along the outer periphery of the metal plate and that faces the bottom surface area.Type: ApplicationFiled: December 3, 2018Publication date: March 4, 2021Inventors: Hirotaka OOMORI, Takashi TSUNO
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Patent number: 10916531Abstract: A semiconductor module according to an embodiment includes a circuit substrate, a first vertical transistor having a first main electrode pad facing and coupled to a first input interconnect pattern of the circuit substrate, and having a first gate electrode pad coupled to a first control interconnect pattern of the circuit substrate, a second vertical transistor having a fourth main electrode pad facing and coupled to a second input interconnect pattern of the circuit substrate, and having a second gate electrode pad facing and coupled to a second control interconnect pattern of the circuit substrate, a surge voltage absorbing device connecting the first and second input interconnect patterns to absorb surge voltage, and a plate member connecting a second main electrode pad of the first vertical transistor and a third main electrode pad of the second vertical transistor.Type: GrantFiled: August 7, 2017Date of Patent: February 9, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hirotaka Oomori
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Publication number: 20210013130Abstract: A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.Type: ApplicationFiled: January 22, 2019Publication date: January 14, 2021Inventors: Kenichi SAWADA, Jiro SHINKAI, So TANAKA, Hirotaka OOMORI
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Publication number: 20200395255Abstract: A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surType: ApplicationFiled: January 15, 2019Publication date: December 17, 2020Inventors: Tatsushi KANEDA, Yoshisumi KAWABATA, So TANAKA, Hirotaka OOMORI