Abstract: The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.

Abstract: A nitride semiconductor device includes a passivation layer which has a first opening and a second opening, and which covers an electron supply layer, a gate layer, and a gate electrode. The passivation layer includes: a first insulation layer formed on at least a portion of the electron supply layer positioned, in plan view, between the first opening and gate layer; and a second insulation layer which covers the gate layer and gate electrode, and which is formed on the electron supply layer positioned, in plan view, between the second opening and gate layer. The second insulation layer is formed from a material having a Young's modulus lower than that of the first insulation layer.

Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 13 that constitutes an electron transit layer, a second nitride semiconductor layer 14 that is formed on the first nitride semiconductor layer and constitutes an electron supply layer, a nitride semiconductor gate layer 15 that is disposed on the second nitride semiconductor layer, has a ridge portion 15A at least at a portion thereof, and contains an acceptor type impurity, a gate electrode 4 that is disposed at least on the ridge portion of the nitride semiconductor gate layer, a source electrode 3 that is disposed on the second nitride semiconductor layer and has a source principal electrode portion 3A parallel to the ridge portion, and a drain electrode 5 that is disposed on the second nitride semiconductor layer and has a drain principal electrode portion 5A parallel to the ridge portion.

Abstract: A nitride semiconductor module includes a nitride semiconductor device, forming a transistor, and a control circuit. The nitride semiconductor device includes a control electrode arranged on a passivation layer between gate and drain electrodes. The control circuit generates first and second control voltages. The first control voltage, which shifts between a first voltage level and a lower second voltage level, controls a voltage applied between the gate and source electrodes. The second control voltage, which shifts between a third voltage and a lower fourth voltage level, is applied between the control and source electrodes. The control circuit generates the first and second control voltages during a turn-off operation of the transistor so that a shifting completion time of the second control voltage from the third to fourth voltage level is earlier than that of the first control voltage from the first to second voltage level.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: The present invention provides a nitride semiconductor device, including an insulating substrate, a substrate over the first surface of the insulating substrate, a first lateral transistor over a first region of the substrate, wherein the first lateral transistor includes a first nitride semiconductor layer formed over the substrate, and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, and a second lateral transistor over a second region of the substrate, wherein the second lateral transistor includes a second nitride semiconductor layer formed over the substrate, and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, and a separation trench formed over a third region, wherein the third region is between the first region and the second region.

Abstract: A nitride semiconductor device includes a source electrode that is in contact with a second nitride semiconductor layer via a first opening portion and with which a portion is formed above a passivation film and a drain electrode that is in contact with the second nitride semiconductor layer via a second opening portion and with which a portion is formed above the passivation film such as to oppose the source electrode across a ridge portion, and the third nitride semiconductor layer has, between a ridge portion side end of the first opening portion and a first opening portion end of the ridge portion and/or between a ridge portion side end of the drain electrode and a second opening portion end of the ridge portion, an extension portion that extends outward from a portion below a thickness intermediate position of at least one side surface of the ridge portion.

Abstract: A nitride semiconductor device includes an electron transit layer formed from a nitride semiconductor, an electron supply layer formed on the electron transit layer from a nitride semiconductor having a larger band gap than the electron transit layer, a gate layer formed on the electron supply layer from a nitride semiconductor including an acceptor impurity, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and including first and second openings separated in a first direction, the gate layer being disposed therebetween, a source electrode contacting the electron supply layer through the first opening, a drain electrode contacting the electron supply layer through the second opening, and an auxiliary electrode formed above the electron supply layer, directly covered by the passivation layer, and disposed between the gate electrode and the drain electrode in plan view.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: An apparatus includes a control device configured to serve as a principal controlling agent in an electric power conversion device incorporating a switching circuit configured to be a bidirectional inverter. The control device is configured to subtract, from a reference signal that is determined in accordance with an operation mode of the electric power conversion device, a multiplied signal obtained by multiplying a control-target current of the switching circuit by a prescribed coefficient to generate, based on a result of the subtraction, a control signal for controlling the bidirectional inverter.

Abstract: A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.

Abstract: Disclosed is a nitride semiconductor apparatus including a substrate, a first nitride semiconductor layer disposed above the substrate, and constituting an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, and constituting an electron supply layer, a nitride semiconductor gate layer disposed on the second nitride semiconductor layer having a ridge portion at at least an area thereof, and containing an acceptor-type impurity, a gate electrode disposed on the ridge portion, a source electrode and a drain electrode disposed opposite to each other, with the ridge portion interposed therebetween, on the second nitride semiconductor layer, and a strip-shaped insulator disposed between the substrate and a surface layer portion of the first nitride semiconductor layer, and extending along a length direction of the ridge portion when viewed in plan.

Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

Abstract: A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.

Abstract: A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

Abstract: There is provided a nitride semiconductor device that includes a first nitride semiconductor layer configured as an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer, a ridge-shaped nitride semiconductor gate layer disposed on the second nitride semiconductor layer and including an acceptor-type impurity, and a gate electrode formed on the nitride semiconductor gate layer. The gate electrode includes a first metal film that is formed on the nitride semiconductor gate layer and is mainly made of Ti, and a second metal film that is formed on the first metal film and is made of TiN.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer constituting an electron transit layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and constituting an electron supply layer; a ridge-shaped gate portion formed on the second nitride semiconductor layer; and a source electrode and a drain electrode disposed on the second nitride semiconductor layer so as to face each other with the ridge-shaped gate portion interposed therebetween, wherein the ridge-shaped gate portion includes: a nitride semiconductor gate layer containing acceptor-type impurities and disposed on the second nitride semiconductor layer; a gate metal film disposed on the nitride semiconductor gate layer; a gate insulating film formed on the gate metal film; and a gate electrode capacitively-coupled to the gate metal film by the gate insulating film.

Abstract: A semiconductor device of an aspect of the disclosure includes a switching element, a substrate, a front electroconductive layer, first through third terminals and a sealing resin. The first through third terminals project toward the same side from the sealing resin along a first direction crossing the substrate thickness direction. The first through third terminals are spaced apart in a second direction crossing the thickness and first directions. The first terminal is at an outermost side in the second direction among the first through third terminals. The sealing resin has root-side and tip-side parts. The root-side part is between the first and third terminals in the second direction and offset in the first direction toward the switching element side of the first and third terminals. The tip-side part is offset in the first direction toward the tip side of the first and third terminals exposed from the sealing resin.

Abstract: The present invention provides a semiconductor device for reducing parasitic inductance. The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad, a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.