Patents by Inventor Hirotaka Shimoda
Hirotaka Shimoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9501113Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.Type: GrantFiled: June 20, 2011Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kyouhei Kouno, Shinichi Nakatsu, Kazuyo Yamaguchi, Kimiharu Eto, Kuniyasu Ishihara, Hirotaka Shimoda, Yuusuke Urakawa, Seiya Indo
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Patent number: 9342097Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.Type: GrantFiled: June 4, 2014Date of Patent: May 17, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta
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Publication number: 20140289547Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.Type: ApplicationFiled: June 4, 2014Publication date: September 25, 2014Applicant: Renesas Electronics CorporationInventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta
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Patent number: 8749224Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.Type: GrantFiled: July 21, 2011Date of Patent: June 10, 2014Assignee: Renesas Electronics CorporationInventors: Rumi Matsushita, Shinichi Nakatsu, Kuniyasu Ishihara, Kimiharu Eto, Seiya Indo, Hirotaka Shimoda
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Patent number: 8751842Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.Type: GrantFiled: May 13, 2011Date of Patent: June 10, 2014Assignee: Renesas Electronics CorporationInventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta
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Publication number: 20120025805Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.Type: ApplicationFiled: July 21, 2011Publication date: February 2, 2012Inventors: Rumi MATSUSHITA, Shinichi NAKATSU, Kuniyasu ISHIHARA, Kimiharu ETO, Seiya INDO, Hirotaka SHIMODA
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Publication number: 20110313700Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.Type: ApplicationFiled: June 20, 2011Publication date: December 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kyouhei KOUNO, Shinichi NAKATSU, Kazuyo YAMAGUCHI, Kimiharu ETO, Kuniyasu ISHIHARA, Hirotaka SHIMODA, Yuusuke URAKAWA, Seiya INDO
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Publication number: 20110285429Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.Type: ApplicationFiled: May 13, 2011Publication date: November 24, 2011Applicant: Renesas Electronics CorporationInventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta
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Patent number: 6636066Abstract: In measuring the resistance value of an output buffer, a supply voltage is supplied to a first P-channel transistor in its source through an ammeter provided within an IC tester, a ground potential is supplied from the IC tester to a first N-channel transistor in its source, and a voltmeter provided within the IC tester is connected to a first external output terminal. A test control signal is then brought to a high level. Further, a test signal of a plurality of bits, which brings only a first test control signal to a high level while brining the remaining 2nd to nth test control signals to a low level, is input into a decoder. As a result, the first P-channel transistor and the first N-channel transistor are brought to an ON state, while 2nd to nth external output terminals are brought to a high-impedance state.Type: GrantFiled: December 5, 2001Date of Patent: October 21, 2003Assignee: NEC Electronics CorporationInventor: Hirotaka Shimoda
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Publication number: 20020101249Abstract: In measuring the resistance value of an output buffer, a supply voltage is supplied to a first P-channel transistor in its source through an ammeter provided within an IC tester, a ground potential is supplied from the IC tester to a first N-channel transistor in its source, and a voltmeter provided within the IC tester is connected to a first external output terminal. A test control signal is then brought to a high level. Further, a test signal of a plurality of bits, which brings only a first test control signal to a high level while brining the remaining 2nd to nth test control signals to a low level, is input into a decoder. As a result, the first P-channel transistor and the first N-channel transistor are brought to an ON state, while 2nd to nth external output terminals are brought to a high-impedance state.Type: ApplicationFiled: December 5, 2001Publication date: August 1, 2002Applicant: NEC CorporationInventor: Hirotaka Shimoda