Abstract: There is provided an IEEE 1394 transmitter for transmitting a plurality of audio data contents, having an audio data generator configured to sample the plurality of audio data contents sequentially to generate format data of an audio data content; and an IEEE 1394 transmission controller configured to add an IEEE 1394 header packet to the format data of the audio data content.

Abstract: A data transfer device comprises a unit for collecting data of a control state by monitoring the control state of a circuit which controls communications protocols within the local device, and a unit for detecting an abnormal state of a data transfer based on the collected state data.

Abstract: A data transfer device arranged in a node for connection in compliance with a communication standard. The data transfer device includes a request signal generation circuit for generating request signals defined by the communication standard with different levels of priority. A determination circuit determines the request signal having the highest level of priority. Priority is given to the transfer of data corresponding to the request signal determined to have the highest level of priority by the determination circuit. A top priority request signal generation unit generates a top priority request signal that differs from the request signals defined by the communication standard. The determination circuit includes a priority determination table in which the uppermost priority request signal is set to have a level of priority that is higher than the levels of priority of the plurality of existing request signals.

Abstract: An interface circuit that can disconnect a loop connection among nodes. The interface circuit includes ports, which are connected to bus cables, a state machine and a port controller, which is connected to the ports and the state machine. The state machine determines that a loop connection exists when a process in a predetermined state has been stacked for a predetermined time. When a loop connection exists, the port controller electrically disconnects a port on the loop.

Abstract: A packet transfer control circuit is a part of a node in a network of nodes, in which packets of data are passed between the nodes. The packets include normal packets and write packets, and each packet includes a header portion and a data portion. The transfer control circuit includes an identification circuit which identifies if the data portion of a write packet is blank and a processor with a memory connected to the identification circuit. If the write packet is blank, as determined by the identification circuit and the processor is holding data for transmission to another node, the processor puts the data into the data portion of the packet, zero fills if the there is not enough data to fill the data portion, updates the header with the new addressee, and then passes the write packet on to the other nodes.

Abstract: A data transfer device comprises a unit for collecting data of a control state by monitoring the control state of a circuit which controls communications protocols within the local device, and a unit for detecting an abnormal state of a data transfer based on the collected state data.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: An IEEE 1394 compliant bus controller transfers data packets between connected nodes. The controller includes a processor which divides a series of data into blocks and then stores the blocks in multiple packets (one block per packet). The packets are then transferred over the bus from a source node to a destination node at equal intervals until the entire series of data has been transferred. An initialization prohibition unit prohibits initialization of the nodes during the data transfer which may be caused, for example, by hot plugging (connecting a new node to the bus) during the data transfer.

Abstract: To reduce power consumption by increasing amplifying efficiency in a low power mode, there is provided a radio communication apparatus in which each of field effect transistors of a radio frequency power module in a multi-stage configuration is controlled by an APC circuit based on a power level instruction signal, and in which a correction circuit is incorporated between the gate of a final stage transistor and the APC circuit to apply a linear gate voltage to the final stage transistor when a High level signal based on the power level instruction signal is applied and to provide a maximum gate voltage of the final stage transistor which is equal to or lower than the gate voltages of other transistors and whose rate of increase relative to the output voltage of the APC circuit gradually reduces when a Low level signal based on the power instruction signal is applied.

Abstract: An interface circuit that can disconnect a loop connection among nodes. The interface circuit includes ports, which are connected to bus cables, a state machine and a port controller, which is connected to the ports and the state machine. The state machine determines that a loop connection exists when a process in a predetermined state has been stacked for a predetermined time. When a loop connection exists, the port controller electrically disconnects a port on the loop.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: To reduce power consumption by increasing amplifying efficiency in a low power mode, there is provided a radio communication apparatus in which each of field effect transistors of a radio frequency power module in a multi-stage configuration is controlled by an APC circuit based on a power level instruction signal, and in which a correction circuit is incorporated between the gate of a final stage transistor and the APC circuit to apply a linear gate voltage to the final stage transistor when a High level signal based on the power level instruction signal is applied and to provide a maximum gate voltage of the final stage transistor which is equal to or lower than the gate voltages of other transistors and whose rate of increase relative to the output voltage of the APC circuit gradually reduces when a Low level signal based on the power instruction signal is applied.

Abstract: To reduce power consumption by increasing amplifying efficiency in a low power mode, there is provided a radio communication apparatus in which each of field effect transistors of a radio frequency power module in a multi-stage configuration is controlled by an APC circuit based on a power level instruction signal, and in which a correction circuit is incorporated between the gate of a final stage transistor and the APC circuit to apply a linear gate voltage to the final stage transistor when a High level signal based on the power level instruction signal is applied and to provide a maximum gate voltage of the final stage transistor which is equal to or lower than the gate voltages of other transistors and whose rate of increase relative to the output voltage of the APC circuit gradually reduces when a Low level signal based on the power instruction signal is applied.

Abstract: An interface circuit including an interface controller operated by at least a system power supply or an external power supply. A switch is connected between an interface controller and a system power circuit for conducting system power. The interface controller includes a control signal generating circuit for generating a control signal that closes the switch at a timing that does not affect data transmission performed by the interface circuit in accordance with a trigger signal, which indicates that the system power has gone on. Similarly, the switch is opened at a time when data transmission will not be affected.

Abstract: To reduce power consumption by increasing amplifying efficiency in a low power mode, there is provided a radio communication apparatus in which each of field effect transistors of a radio frequency power module in a multi-stage configuration is controlled by an APC circuit based on a power level instruction signal, and in which a correction circuit is incorporated between the gate of a final stage transistor and the APC circuit to apply a linear gate voltage to the final stage transistor when a High level signal based on the power level instruction signal is applied and to provide a maximum gate voltage of the final stage transistor which is equal to or lower than the gate voltages of other transistors and whose rate of increase relative to the output voltage of the APC circuit gradually reduces when a Low level signal based on the power instruction signal is applied.