Abstract: An image data processing device includes a first integrated circuit, a second integrated circuit, and a third integrated circuit. The first integrated circuit includes a first image processing circuit for first image processing for image data in a first memory, and a first serial interface for direct memory access transfer between the first memory and a third memory. The second integrated circuit includes a second image processing circuit for second image processing for image data in a second memory, and a second serial interface for direct memory access transfer between the second memory and the third memory. The third integrated circuit includes a third image processing circuit for third image processing for image data in the third memory, and a third serial interface for direct memory access transfer between the third memory and the first memory, and between the third memory and the second memory.

Abstract: An image data processing device includes a first integrated circuit, a second integrated circuit, and a third integrated circuit. The first integrated circuit includes a first image processing circuit for first image processing for image data in a first memory, and a first serial interface for direct memory access transfer between the first memory and a third memory. The second integrated circuit includes a second image processing circuit for second image processing for image data in a second memory, and a second serial interface for direct memory access transfer between the second memory and the third memory. The third integrated circuit includes a third image processing circuit for third image processing for image data in the third memory, and a third serial interface for direct memory access transfer between the third memory and the first memory, and between the third memory and the second memory.

Abstract: A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language.