Abstract: A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

Abstract: A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

Abstract: Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit.

Abstract: A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

Abstract: A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.