Abstract: A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.

Abstract: A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.

Abstract: A semiconductor device is provided having an internal circuit to be tested, a redundancy circuit used when detecting a defective part in the internal circuit, and a switching unit connected to the internal circuit and the redundancy circuit. The switching unit switches wiring in order to ensure proper operation of the semiconductor. A test unit is connected to the internal circuit for testing for the internal circuit. An operation environment change unit is connected to the internal circuit, wherein for changing an environment of the internal circuit when during testing. According to the present invention, testing of semiconductor devices can be performed under an actual environment so that a defective part can be detected under the actual operation environment. Moreover, it is possible to widen the range of guaranteed operation of semiconductor devices when a plurality of tests are performed under a plurality of operation environments.