Abstract: A plurality of variable load capacitance circuits is connected to each node between adjacent delay circuits of a ring oscillator, and changes load capacitance according to an external control signal. The control circuit adjusts timing the control signal is inputted to these variable load capacitance circuits, using a clock signal of one or more nodes of the ring oscillator.

Abstract: A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first clock successively delayed through the first delay elements and hold a digital value representing a relative phase difference, in accordance with the second clock successively delayed through the second delay elements. Therefore, the phase detection resolution of the digital phase detector can be improved.

Abstract: A plurality of variable load capacitance circuits is connected to each node between adjacent delay circuits of a ring oscillator, and changes load capacitance according to an external control signal. The control circuit adjusts timing the control signal is inputted to these variable load capacitance circuits, using a clock signal of one or more nodes of the ring oscillator.

Abstract: A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first clock successively delayed through the first delay elements and hold a digital value representing a relative phase difference, in accordance with the second clock successively delayed through the second delay elements. Therefore, the phase detection resolution of the digital phase detector can be improved.