Patents by Inventor Hiroto Misawa
Hiroto Misawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210206965Abstract: An object of the present invention is to provide a resin composition which is capable of melt molding multiple times and thus has excellent recyclability. The resin composition of the present invention contains a polylactic acid (A), an acid-modified aliphatic polyester-based resin (B) and a polyvinyl alcohol-based resin (C), in which a content of the acid-modified aliphatic polyester-based resin (B) is 0.3 to 15 parts by weight with respect to 100 parts by weight of the polylactic acid (A) and a content of the polyvinyl alcohol-based resin (C) is 0.3 to 10 parts by weight with respect to 100 parts by weight.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Applicant: Mitsubishi Chemical CorporationInventors: Hiroto MISAWA, Yuya KANAMORI, Norihito SAKAI
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Publication number: 20200231730Abstract: An object of the present invention is to provide a biodegradable acid-modified polyester resin, from which a laminate including a polyvinyl alcohol resin layer and a biodegradable resin layer, having little roughness at an adhesive layer interface between the two layers, and excellent in both appearance and adhesiveness can be obtained. The present invention relates to a biodegradable acid-modified polyester resin having an acid value of 2.0 mg·KOH/g to 6.5 mg·KOH/g.Type: ApplicationFiled: February 28, 2020Publication date: July 23, 2020Applicant: Mitsubishi Chemical CorporationInventors: Hiroto MISAWA, Noriaki KUROKAWA, Masahiko TANIGUCHI
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Patent number: 10141399Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region. The first insulating layer is provided around at least a portion of the first semiconductor region and at least a portion of the second semiconductor region. The first insulating layer contacts the second semiconductor region. The first insulating region is provided around at least a portion of the first insulating layer.Type: GrantFiled: September 7, 2015Date of Patent: November 27, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Masanobu Tsuchitani, Hiroto Misawa, Akira Ezaki, Tatsuya Shiraishi
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Publication number: 20160276430Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region. The first insulating layer is provided around at least a portion of the first semiconductor region and at least a portion of the second semiconductor region. The first insulating layer contacts the second semiconductor region. The first insulating region is provided around at least a portion of the first insulating layer.Type: ApplicationFiled: September 7, 2015Publication date: September 22, 2016Inventors: Hideki Okumura, Masanobu Tsuchitani, Hiroto Misawa, Akira Ezaki, Tatsuya Shiraishi
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Patent number: 9142667Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: September 12, 2014Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20150028413Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: ApplicationFiled: September 12, 2014Publication date: January 29, 2015Inventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
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Patent number: 8859365Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: March 3, 2014Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20140179075Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
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Patent number: 8710582Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: March 14, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Publication number: 20140035105Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming semiconductor layers in a plurality of first regions on a semiconductor wafer. The plurality of first regions are separated from each other. The method includes forming elements in the semiconductor layers. The method includes bonding an insulating plate made of an inorganic material in a second region on the semiconductor wafer. The second region excludes the first regions. The method includes performing singulation for each of the semiconductor layers by cutting the semiconductor wafer and the insulating plate along a dicing line configured to pass through only the second region.Type: ApplicationFiled: March 18, 2013Publication date: February 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira KOMATSU, Kaori FUSE, Hiroto MISAWA
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Publication number: 20130153995Abstract: A semiconductor device includes a first region with second conductivity type formed over a semiconductor layer with first conductivity type. On this first region, the second region of the first conductivity type is selectively provided. On the same first region, a third region of second conductivity type is also selectively provided and is adjoined to the second region. The first control electrode is provided within a trench located deeper than the first side of the second region compared to the first region. The first control electrode includes a part opposed to the first and second regions separated by a first insulator, and a second part opposed to the semiconductor layer separated by a thicker second insulator. Inside the trench, the second control electrode is provided between the trench bottom and the first control electrode. The second control electrode is opposed to the semiconductor layer through a third insulator.Type: ApplicationFiled: September 7, 2012Publication date: June 20, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroto MISAWA, Hideki Okumura
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Publication number: 20130069146Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: ApplicationFiled: March 14, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hideki OKUMURA, Hiroto MISAWA, Takahiro KAWANO
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Patent number: 8173509Abstract: A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.Type: GrantFiled: March 1, 2010Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Takayoshi Nogami, Hiroto Misawa
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Publication number: 20100151644Abstract: A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.Type: ApplicationFiled: March 1, 2010Publication date: June 17, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki OKUMURA, Takayoshi Nogami, Hiroto Misawa
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Patent number: 7700998Abstract: A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.Type: GrantFiled: June 30, 2008Date of Patent: April 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Takayoshi Nogami, Hiroto Misawa
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Publication number: 20090014788Abstract: A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.Type: ApplicationFiled: June 30, 2008Publication date: January 15, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki OKUMURA, Takayoshi Nogami, Hiroto Misawa
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Patent number: 5432125Abstract: In a method of manufacturing a semiconductor apparatus, a resist is coated on a semiconductor substrate and baked. The resist is exposed with an electron beam, and an invertedly tapered opening is formed. Recess etching is performed on the semiconductor substrate through the opening. An electrode is formed at a location determined by the recess etching.Type: GrantFiled: July 18, 1994Date of Patent: July 11, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Misawa, Hitoshi Tsuji
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Patent number: 5385851Abstract: In a method of manufacturing a semiconductor apparatus, a resist is coated on a semiconductor substrate and baked. The resist is exposed with an electron beam, and an invertedly tapered opening is formed. Recess etching is performed on the semiconductor substrate through the opening. An electrode is formed at a location determined by the recess etching.Type: GrantFiled: June 14, 1993Date of Patent: January 31, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Misawa, Hitoshi Tsuji