Patents by Inventor Hiroto Yasuura

Hiroto Yasuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6606532
    Abstract: A method of manufacturing a system LSI is disclosed, in which the running cost such the power consumption is not increased even in the case where the hardware, and software are reused for reducing the manufacturing cost. The method for manufacturing a system LSI, having at least a processor and a memory in a single chip, comprises the steps of preparing a system LSI in the stage where a preset common process has been complete, determining the working area for activating an application program mounted on the system LSI based on the datapath width of the processor and the word length and the number of words of the memory used for activating the application program, and completing the manufacture of the system LSI in such a manner that no power is supplied to the area other than the working area. In this way, the hardware and software are reused without increasing the power consumption or other running costs.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: August 12, 2003
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroto Yasuura, Akihiko Inoue
  • Patent number: 6384624
    Abstract: The present invention has as an object thereof to provide a logical operational circuit which is capable of realizing, with present semiconductor manufacturing technology, logical functions, the realization of which has been extremely difficult heretofore as a result of constraints in the voltage levels which are to be discriminated on the floating gate of the neuMOS.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: May 7, 2002
    Inventors: Hiroto Yasuura, Kenjiro Ike