Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

Abstract: There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of the IDE device side is low. A RAID system (10) which is a storage system in which a RAID controller (11) connected to an ATA host and a plurality of IDE devices (12A to 12D, and 22A to 22D) are connected by an IDE bus, characterized in that at least two or more IDE devices are connected to one channel of the IDE bus and said RAID controller and each of said IDE devices are connected by a common data bus and a common address bus within the same channel.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of the IDE device side is low. A RAID system (10) which is a storage system in which a RAID controller (11) connected to an ATA host and a plurality of IDE devices (12A to 12D, and 22A to 22D) are connected by an IDE bus, characterized in that at least two or more IDE devices are connected to one channel of the IDE bus and said RAID controller and each of said IDE devices are connected by a common data bus and a common address bus within the same channel.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: A method of installing a software program in a host device, which is required for the host device to communicate with a peripheral device. The method includes the steps of coupling the host device to the peripheral device, which contains the software program stored in a memory device contained in the peripheral device, utilizing a USB serial interface; uploading the software program from the peripheral device to the host device; and installing the software program in the host device thereby allowing communication between the host device and the peripheral device.

Abstract: Disclosed is an apparatus and method for transferring data from a directly from peripheral computer device to a computer via a universal serial bus. The disclosed method and apparatus can also compress the transferred data. The apparatus can include a Serial Interface Engine (SIE) connected with the computer and having a latch and a First-In-First-Out memory (FIFO) connected to the latch of the SIE. The FIFO temporarily stores data from the peripheral computer device and transfers the data to the latch of the SIE. A read input of the latch is driven at a first clock frequency and an output of the FIFO is driven at a second clock frequency. The second clock frequency is at least intermittently higher than the first clock frequency. Thus, a portion of the data placed on the output of the FIFO at the second clock frequency is not read into the latch. This allows data to be compressed as it is transferred from the FIFO to the SIE.