Patents by Inventor Hirotoki Yokoi
Hirotoki Yokoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901211Abstract: A semiconductor-processing tape, for use in dividing an adhesive layer along semiconductor chips by expansion, having a base material film, a removable adhesive layer, and an adhesive layer, in this order, wherein the base material film has the stress values in MD and TD at the time of 5%-elongation of 5 MPa or, more, the tensile strength values in MD and TD at the time of 5%-elongation of 10 to 30 N/25 mm, and the thickness of from 70 to 150 ?m, and wherein the adhesive layer has a thickness of 40 ?m or more and the storage elastic modulus at 25° C. of 2000 MPa or less.Type: GrantFiled: June 5, 2019Date of Patent: February 13, 2024Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki Yokoi, Yukihiro Matsubara
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Patent number: 11707804Abstract: A mask-integrated surface protective tape, containing: a substrate film; a temporary-adhesive layer provided on the substrate film; and a mask material layer provided on the temporary-adhesive layer; wherein the mask material layer and the temporary-adhesive layer each contain a (meth)acrylic copolymer; and wherein the mask-integrated surface protective tape is used for a method of producing a semiconductor chip utilizing a plasma-dicing.Type: GrantFiled: January 11, 2018Date of Patent: July 25, 2023Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki Yokoi, Tomoaki Uchiyama, Yoshifumi Oka
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Patent number: 11282736Abstract: A mask-integrated surface protective tape with a release liner, containing: a base film, a temporary-adhesive layer, a release film, a mask material layer, and a release liner, in this order, wherein the release film and the release liner each have one release-treated surface, and the release-treated surfaces of the release film and the release liner each are in contact with the mask material layer, and wherein the peeling strength between the release liner and the mask material layer is smaller than the peeling strength between the release film and the mask material layer.Type: GrantFiled: September 26, 2019Date of Patent: March 22, 2022Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Yukihiro Matsubara, Hirotoki Yokoi
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Patent number: 10971387Abstract: A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN/m to 48.0 mN/m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 ?m to 2.0 ?m when measured in conformity to JIS B0601, (a) a specific laminating step; (b) a specific peeling step; (c) a specific plasma-dicing step; and (d) a specific ashing step.Type: GrantFiled: February 26, 2019Date of Patent: April 6, 2021Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Yusuke Goto, Hirotoki Yokoi
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Patent number: 10916439Abstract: A mask-integrated surface protective film, containing: a substrate film, and a mask material layer provided on the substrate film; wherein the mask material layer is an ethylene-vinyl acetate copolymer resin, an ethylene-methyl acrylate copolymer resin, or an ethylene-butyl acrylate copolymer resin; and wherein the thickness of the mask material layer is 50 ?m or less.Type: GrantFiled: January 11, 2018Date of Patent: February 9, 2021Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki Yokoi, Tomoaki Uchiyama, Yoshifumi Oka
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Patent number: 10916441Abstract: A surface side is irradiated with an SF6 gas plasma to etch a semiconductor wafer which has been peeled off in street portions, and divide the semiconductor wafer into a plurality of individual semiconductor chips. A removing agent is subsequently supplied from the surface side. At that time, it is preferable that the semiconductor wafer divided into the plurality of chips is rotated at high speed. Accordingly, a mask material layer remaining on the surface is removed by the removing agent. Moreover, the removing agent is preferably an organic solvent, and more preferably, methyl ethyl ketone, ethanol, and ethyl acetate, or a combination of these.Type: GrantFiled: August 13, 2019Date of Patent: February 9, 2021Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Tomoaki Uchiyama, Akira Akutsu, Hirotoki Yokoi
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Publication number: 20200017728Abstract: A mask-integrated surface protective tape with a release liner, containing: a base film, a temporary-adhesive layer, a release film, a mask material layer, and a release liner, in this order, wherein the release film and the release liner each have one release-treated surface, and the release-treated surfaces of the release film and the release liner each are in contact with the mask material layer, and wherein the peeling strength between the release liner and the mask material layer is smaller than the peeling strength between the release film and the mask material layer.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Yukihiro MATSUBARA, Hirotoki YOKOI
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Publication number: 20190371618Abstract: A surface side is irradiated with an SF6 gas plasma to etch a semiconductor wafer which has been peeled off in street portions, and divide the semiconductor wafer into a plurality of individual semiconductor chips. A removing agent is subsequently supplied from the surface side. At that time, it is preferable that the semiconductor wafer divided into the plurality of chips is rotated at high speed. Accordingly, a mask material layer remaining on the surface is removed by the removing agent. Moreover, the removing agent is preferably an organic solvent, and more preferably, methyl ethyl ketone, ethanol, and ethyl acetate, or a combination of these.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventors: Tomoaki Uchiyama, Akira Akutsu, Hirotoki Yokoi
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Publication number: 20190311937Abstract: A semiconductor-processing tape, for use in dividing an adhesive layer along semiconductor chips by expansion, having a base material film, a removable adhesive layer, and an adhesive layer, in this order, wherein the base material film has the stress values in MD and TD at the time of 5%-elongation of 5 MPa or, more, the tensile strength values in MD and TD at the time of 5%-elongation of 10 to 30 N/25 mm, and the thickness of from 70 to 150 ?m, and wherein the adhesive layer has a thickness of 40 ?m or more and the storage elastic modulus at 25° C. of 2000 MPa or less.Type: ApplicationFiled: June 5, 2019Publication date: October 10, 2019Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki YOKOI, Yukihiro MATSUBARA
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Publication number: 20190198378Abstract: A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN/m to 48.0 mN/m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 ?m to 2.0 ?m when measured in conformity to JIS B0601, (a) a specific laminating step; (b) a specific peeling step; (c) a specific plasma-dicing step; and (d) a specific ashing step.Type: ApplicationFiled: February 26, 2019Publication date: June 27, 2019Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Yusuke GOTO, Hirotoki YOKOI
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Patent number: 10307866Abstract: A method of producing a semiconductor chip, including the following steps (a) to (d): (a) a step of, in the state of having laminated a mask-integrated surface protective tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the semiconductor wafer; laminating a wafer fixing tape on the backing-face side of the ground semiconductor wafer; and supporting and fixing the wafer to a ring flame; (b) a step of, after peeling the surface protective tape thereby to expose the mask material layer on top, forming an opening of a street of the semiconductor wafer; (c) a plasma dicing step of segmentalizing the semiconductor wafer by a plasma irradiation to singulate it into semiconductor chips; and (d) an ashing step of removing the mask material layer by the plasma irradiation.Type: GrantFiled: January 11, 2018Date of Patent: June 4, 2019Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki Yokoi, Tomoaki Uchiyama, Yoshifumi Oka
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Publication number: 20180226359Abstract: A mask-integrated surface protective tape, containing: a substrate film; a temporary-adhesive layer provided on the substrate film; and a mask material layer provided on the temporary-adhesive layer; wherein the mask material layer and the temporary-adhesive layer each contain a (meth)acrylic copolymer; and wherein the mask-integrated surface protective tape is used for a method of producing a semiconductor chip utilizing a plasma-dicing.Type: ApplicationFiled: January 11, 2018Publication date: August 9, 2018Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki YOKOI, Tomoaki UCHIYAMA, Yoshifumi OKA
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Publication number: 20180185964Abstract: A method of producing a semiconductor chip, including the following steps (a) to (d): (a) a step of, in the state of having laminated a mask-integrated surface protective tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the semiconductor wafer; laminating a wafer fixing tape on the backing-face side of the ground semiconductor wafer; and supporting and fixing the wafer to a ring flame; (b) a step of, after peeling the surface protective tape thereby to expose the mask material layer on top, forming an opening of a street of the semiconductor wafer; (c) a plasma dicing step of segmentalizing the semiconductor wafer by a plasma irradiation to singulate it into semiconductor chips; and (d) an ashing step of removing the mask material layer by the plasma irradiation.Type: ApplicationFiled: January 11, 2018Publication date: July 5, 2018Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki YOKOI, Tomoaki UCHIYAMA, Yoshifumi OKA
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Publication number: 20180158691Abstract: A mask-integrated surface protective film, containing: a substrate film, and a mask material layer provided on the substrate film; wherein the mask material layer is an ethylene-vinyl acetate copolymer resin, an ethylene-methyl acrylate copolymer resin, or an ethylene-butyl acrylate copolymer resin; and wherein the thickness of the mask material layer is 50 ?m or less.Type: ApplicationFiled: January 11, 2018Publication date: June 7, 2018Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Hirotoki YOKOI, Tomoaki UCHIYAMA, Yoshifumi OKA
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Publication number: 20110014443Abstract: Problem to be Solved by the Invention: To provide a adhesive tape for electronic component fabrication, having extremely high antistatic performance, superior adherence between an antistatic layer and a adhesive layer, does not cause corrosion of a magnetic head that is comprised of a metal such as pure copper or the like, and alumina to occur, and which is easier to be released again.Type: ApplicationFiled: December 10, 2008Publication date: January 20, 2011Applicant: The Furukawa Electric Co., LtdInventors: Hirotoki Yokoi, Akira Suda, Syouzou Yano, Shinichi Ishiwata