Patents by Inventor Hirotoshi Kubo
Hirotoshi Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230296699Abstract: Disclosed herein is a Hall sensor including a Hall element having a first principal surface, and a first magnetic body arranged on a side of the first principal surface, in which the first magnetic body has a first surface facing the first principal surface, and an area of a projection surface of the first magnetic body when viewed in plan from an opposite side of the Hall element is larger than an area of the first surface.Type: ApplicationFiled: November 2, 2022Publication date: September 21, 2023Inventor: Hirotoshi Kubo
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Patent number: 8076755Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: GrantFiled: June 6, 2008Date of Patent: December 13, 2011Inventors: Mitsuo Umemoto, Shigehito Matsumoto, Hirotoshi Kubo, Yukari Shirahata, Masamichi Yamamuro, Koujiro Kameyama
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Patent number: 7629644Abstract: An interlayer dielectric film is completely buried in a trench, and failures caused by step coverage is prevented because a source electrode can be formed substantially uniformly on an upper portion of a gate electrode. Also, in the processes of forming a source region, a body region and an interlayer dielectric film, only one mask is necessary so that the device size is reduced to account for placement error of only one mask alignment.Type: GrantFiled: December 29, 2004Date of Patent: December 8, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Masahito Onda, Hirotoshi Kubo, Shouji Miyahara, Hiroyasu Ishida, Hiroaki Saito
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Patent number: 7521306Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: GrantFiled: August 2, 2005Date of Patent: April 21, 2009Assignee: Sanyo Electric Co., LtdInventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Patent number: 7439137Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.Type: GrantFiled: May 6, 2005Date of Patent: October 21, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroyasu Ishida, Hirotoshi Kubo, Shouji Miyahara, Masato Onda
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Publication number: 20080237808Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: ApplicationFiled: June 6, 2008Publication date: October 2, 2008Applicants: Sanyo Electric Co., Ltd., Kanto Semiconductors Co., Ltd.Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Patent number: 7413954Abstract: A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.Type: GrantFiled: September 21, 2005Date of Patent: August 19, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda, Satoshi Iwata, Masamichi Yanagida
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Patent number: 7397128Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: GrantFiled: March 28, 2006Date of Patent: July 8, 2008Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Patent number: 7320916Abstract: When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer.Type: GrantFiled: September 29, 2004Date of Patent: January 22, 2008Assignees: Sanyo Electric Co., Ltd., Gifu Sanyo Electronics Co., Ltd.Inventors: Hirotoshi Kubo, Yasuhiro Igarashi, Masahiro Shibuya
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Publication number: 20070166905Abstract: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.Type: ApplicationFiled: February 22, 2007Publication date: July 19, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masamichi Yanagida, Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda
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Patent number: 7230300Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.Type: GrantFiled: August 31, 2004Date of Patent: June 12, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Masahito Onda, Hirotoshi Kubo, Shouji Miyahara, Hiroyasu Ishida
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Publication number: 20060220178Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.Type: ApplicationFiled: March 28, 2006Publication date: October 5, 2006Inventors: Hirotoshi Kubo, Yukari Shirahata, Shigehito Matsumoto, Masamichi Yamamuro, Koujiro Kameyama, Mitsuo Umemoto
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Publication number: 20060065926Abstract: A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.Type: ApplicationFiled: September 21, 2005Publication date: March 30, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hirotoshi Kubo, Junichiro Tojo, Hiroaki Saito, Masahito Onda, Satoshi Iwata, Masamichi Yanagida
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Publication number: 20060054970Abstract: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat treatment is not performed. The channel layer is allowed to have its impurity concentration substantially uniform in a depth-wise direction of the trenches, by implanting ions of the impurity at plural different times by use of a high-acceleration ion implantation system. Since a second region having almost no influence on a characteristic of the channel layer can be reduced, the channel layer having a minimum necessary depth can be obtained. The trenches are thus made shallow, and accordingly a capacitance can be reduced. Furthermore, an on resistance can be made lower by making an epitaxial layer thinner.Type: ApplicationFiled: September 7, 2005Publication date: March 16, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Masamichi Yanagida, Hirotoshi Kubo, Junichiro Tojo, Hiraoki Saito, Masahito Onda
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Publication number: 20050266642Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: ApplicationFiled: August 2, 2005Publication date: December 1, 2005Inventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Patent number: 6967139Abstract: In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.Type: GrantFiled: July 19, 2004Date of Patent: November 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Makoto Oikawa, Hiroki Etou, Hirotoshi Kubo, Shouji Miyahara
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Publication number: 20050255706Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.Type: ApplicationFiled: May 6, 2005Publication date: November 17, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Hiroyasu Ishida, Hirotoshi Kubo, Shouji Miyahara, Masato Onda
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Patent number: 6939776Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: GrantFiled: November 19, 2001Date of Patent: September 6, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Publication number: 20050167748Abstract: An interlayer dielectric film is completely buried in a trench, and failures caused by step coverage is prevented because a source electrode can be formed substantially uniformly on an upper portion of a gate electrode. Also, in the processes of forming a source region, a body region and an interlayer dielectric film, only one mask is necessary so that the device size is reduced to account for placement error of only one mask alignment.Type: ApplicationFiled: December 29, 2004Publication date: August 4, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Masahito Onda, Hirotoshi Kubo, Shouji Miyahara, Hiroyasu Ishida, Hiroaki Saito
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Publication number: 20050106843Abstract: When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer.Type: ApplicationFiled: September 29, 2004Publication date: May 19, 2005Applicants: Sanyo Electric Co., Ltd., Gifu Sanyo Electronics Co., Ltd.Inventors: Hirotoshi Kubo, Yasuhiro Igarashi, Masahiro Shibuya