Abstract: According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Abstract: An semiconductor integrated circuit has a macro cell, an initial voltage setting unit to generate initial data to be set in the macro cell, and a data wiring section connected between the macro cell and the initial voltage setting unit so that the data wiring section is at a predetermined potential level.

Abstract: A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs.

Abstract: A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs.

Abstract: A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs.

Abstract: According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Abstract: A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs.

Abstract: A MESFET of a GaAs semiconductor device having a p-pocket LDD structure is used for a high-frequency power amplifier of a mobile communication device, in order to decrease current consumption and to increase the continuous operating time of a battery. The high-frequency power amplifier is provided with a gate-bias adjusting feedback element between the drain and gate of the MESFET. Thus, even if there is a great difference between the filled and terminated potentials of the discharge voltage of the battery for supplying electric power to the amplifier, electric power can be supplied near the terminated potential for a long time, so that the mobile communication device can be continuously used for a long time.

Abstract: A high-speed semiconductor integrated circuit device has a main circuit section formed on a substrate, and a capacitance section formed on the substrate to surround the main circuit section. The capacitance section is made up of two conductive layers, an upper layer being insulatively disposed above a lower layer. These layers are applied with a power source voltage and a ground voltage, respectively. High-speed signal lines insulatively traverse the capacitance section and are connected to the main circuit section. The capacitance section is disconnected in the region where each signal transmission line passes, and defines a micro-strip type signal transmission line path structure. A "ladder"-shaped connection pattern is provided at each disconnected portion of the capacitance section, for electrically connecting a conductive layer arranged on one side of the disconnected portion to the corresponding layer arranged on the other side of the disconnected portion.

Abstract: A demultiplexer has a main circuit section obtained by connecting a plurality of 1:2 demultiplexers, each for distributing a time-divisionally multiplexed signal into tow parts, to form a tree-like arrangement, and a clock frequency divider for frequency-dividing an input clock signal to generate frequency-divided signals to be supplied to the 1:2 demultiplexers of the respective stages of the tree-like arrangement. The demultiplexer has a plurality of inverting circuits for arbitrarily inverting the frequency-divided clock signals supplied from the clock frequency divider to the respective stages of the main circuit section in units of stages.