Patents by Inventor Hirotugu Eguchi

Hirotugu Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4799101
    Abstract: A high-density integrated circuit employing different first and second channel types of insulated gate field effect transistors is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of the transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to some of the transistors and being connected to at least one well region on which the first channel type of transistors are formed, and the other of the upper layers being formed of high-conductivity metal.
    Type: Grant
    Filed: December 23, 1986
    Date of Patent: January 17, 1989
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hirotugu Eguchi
  • Patent number: 4635088
    Abstract: An improved semiconductor device operable at a high-speed and with a low power consumption is disclosed. The device comprises a common impurity-doped region, a first insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, a second insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, control means for controlling switching operations of the first and second transistor at the same time and means for deriving an output signal from the common impurity-doped region.
    Type: Grant
    Filed: October 17, 1984
    Date of Patent: January 6, 1987
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hirotugu Eguchi
  • Patent number: 4524377
    Abstract: A high-density integrated circuit employing different first and second channel types of insulated gate field effect transistors is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of the transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to some of the transistors and being connected to at least one well region on which the first channel type of transistors are formed, and the other of the upper layers being formed of high-conductivity metal.
    Type: Grant
    Filed: February 14, 1984
    Date of Patent: June 18, 1985
    Assignee: NEC Corporation
    Inventor: Hirotugu Eguchi