Patents by Inventor Hiroya Shimizu
Hiroya Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050006751Abstract: A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.Type: ApplicationFiled: August 3, 2004Publication date: January 13, 2005Inventors: Hiroya Shimizu, Asao Nishimura, Toshiho Miyamoto, Hideki Tanaka, Hideo Miura
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Patent number: 6828810Abstract: A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.Type: GrantFiled: July 30, 2002Date of Patent: December 7, 2004Assignee: Renesas Technology Corp.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hiroya Shimizu, Naoto Ban, Hideyuki Aoki
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Patent number: 6784533Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: GrantFiled: August 6, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Publication number: 20040145382Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.Type: ApplicationFiled: July 24, 2003Publication date: July 29, 2004Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
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Patent number: 6614246Abstract: The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.Type: GrantFiled: August 28, 2000Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
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Publication number: 20030122550Abstract: A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.Type: ApplicationFiled: July 30, 2002Publication date: July 3, 2003Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hiroya Shimizu, Naoto Ban, Hideyuki Aoki
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Publication number: 20030104641Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.Type: ApplicationFiled: October 17, 2002Publication date: June 5, 2003Applicant: Hitachi, Ltd.Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki
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Publication number: 20030047731Abstract: Realized is a semiconductor device that test can be effectively conducted by the test device even where the semiconductor device is reduced in chip size and hence pad pitch. A plurality of pads are formed on both ends of a semiconductor substrate. An input pad group is arranged at a left end side of the semiconductor device while an input/output pad groups are arranged at a right end side thereof. A BIST circuit is arranged at an upper right area of the semiconductor device, and the pads close to the BIST circuit serve as BIST exclusive pads. Because the area for arranging the pads for BIST is limited due to the increase of input pads and the like and all the pads for BIST cannot be arranged at one end of the semiconductor device, the BIST pads are separately provided in both ends of the semiconductor substrate. Those close to the BIST circuit are provided as exclusive pads while the others are as common-use pads. The pads 3a and 3b are separated to the upper and lower areas of the semiconductor device.Type: ApplicationFiled: August 15, 2002Publication date: March 13, 2003Inventors: Toshio Miyatake, Tatsuya Nagata, Hiroya Shimizu, Ryuji Kohno, Hideyuki Aoki
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Patent number: 6531785Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: GrantFiled: November 20, 2001Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Publication number: 20030015779Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: ApplicationFiled: September 24, 2002Publication date: January 23, 2003Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Publication number: 20020190336Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: ApplicationFiled: August 6, 2002Publication date: December 19, 2002Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Patent number: 6465264Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: GrantFiled: September 1, 2000Date of Patent: October 15, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Publication number: 20020047179Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: ApplicationFiled: November 20, 2001Publication date: April 25, 2002Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Publication number: 20020033707Abstract: Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.Type: ApplicationFiled: August 10, 2001Publication date: March 21, 2002Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Naoto Ban
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Patent number: 6326699Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: GrantFiled: December 8, 2000Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Publication number: 20010000116Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: ApplicationFiled: December 8, 2000Publication date: April 5, 2001Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Patent number: 6211576Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: GrantFiled: September 17, 1999Date of Patent: April 3, 2001Assignee: Hitachi, Ltd.Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Patent number: 5838549Abstract: In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.Type: GrantFiled: January 27, 1997Date of Patent: November 17, 1998Assignee: Hitachi, Ltd.Inventors: Tatsuya Nagata, Hiroya Shimizu, Atsushi Nakamura, Hideshi Fukumoto, Toshio Sugano