Patents by Inventor Hiroya SHIRAKURA

Hiroya SHIRAKURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11416153
    Abstract: A memory system of an embodiment includes a non-volatile memory and a controller configured to control the accessing of the non-volatile memory according to commands from a host device. The controller is configured to set a mode transition time to a value according to a first command received from the host. The controller transitions from a first operating mode to a second operating mode, in which power supply is suspended to a predetermined circuit, when the time since the last command was received from the host device reaches the mode transition time. The controller maintains the second operating mode until another command is received from the host device.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 16, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tetsuya Iwata, Hiroya Shirakura, Shinya Takeda
  • Patent number: 11360676
    Abstract: According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 14, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroya Shirakura, Shinya Takeda
  • Publication number: 20210294509
    Abstract: A memory system of an embodiment includes a non-volatile memory and a controller configured to control the accessing of the non-volatile memory according to commands from a host device. The controller is configured to set a mode transition time to a value according to a first command received from the host. The controller transitions from a first operating mode to a second operating mode, in which power supply is suspended to a predetermined circuit, when the time since the last command was received from the host device reaches the mode transition time. The controller maintains the second operating mode until another command is received from the host device.
    Type: Application
    Filed: September 2, 2020
    Publication date: September 23, 2021
    Inventors: Tetsuya IWATA, Hiroya SHIRAKURA, Shinya TAKEDA
  • Publication number: 20210294504
    Abstract: According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 23, 2021
    Inventors: Hiroya SHIRAKURA, Shinya TAKEDA
  • Patent number: 10884668
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroya Shirakura, Kyoko Shoji, Shinya Takeda
  • Publication number: 20200301610
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 24, 2020
    Inventors: Hiroya SHIRAKURA, Kyoko SHOJI, Shinya TAKEDA